MCS-5 1 Single Chip Microcomputer is a product introduced by INTE Company of America 1980. Typical products are 80 3 1 (there is no program memory inside, which has been eliminated by the market in actual use) and 805 1 (the chip adopts HMOS, and the power consumption is 630mW, which is five times that of 89C5 1). The actual use has been eliminated by the market) and 875 1, until now MCS-5 1 core series compatible single chip microcomputer is still an application.
Mainstream products (such as popular 89S5 1, discontinued 89C5 1, etc. ), the training materials of universities and professional schools are still learning the theoretical basis represented by MCS-5 1
Some documents even refer to 805 1 as MCS-5 1 series single chip microcomputer, which is the most typical representative in the early days. Due to the far-reaching influence of MCS-5 1 single chip microcomputer, many companies have introduced compatible series single chip microcomputer, that is to say, MCS-5 1 kernel has actually become the standard of an 8-bit single chip microcomputer.
Other companies' 5 1 MCU products are compatible with MCS-5 1 kernel. The same program runs on the hardware of various MCU manufacturers, and the results are the same, such as ATMEL's 89C5 1 (discontinued), 89S5 1, PHILIPS (Philips), WINBOND (Winbond) and so on. The discontinued 89C5 1 we often refer to AT89C56544 of ATMEL. At the same time, many functions have been enhanced on the original basis, such as clock. Better still, the original ROM (write once) is taken from Flash (the contents of the program memory can be rewritten at least 1000 times), and the performance of AT89C5 1 is already very superior to that of 805 1.
However, in terms of marketization, 89C5 1 has been challenged by PIC MCU camp. The most fatal defect of 89C5 1 is that it doesn't support ISP (online update program) function, and new functions such as ISP function must be added to better continue the legend of MCS-5 1. In this context, 89S5 1 replaced 89C5 1. Now, 89S5 1 has become the new favorite in the practical application market. Atmel, which has the largest market share, has been discontinued and will be replaced by AT89S5 1. 89S5 1 inch
The process has been improved. 89S5 1 adopts the new technology of 0.35, which reduces the cost, improves the function and increases the competitiveness. 89SXX can be compatible with 5 1 series chips such as 89CXX. The 89C5 1 seen in the market is actually a huge inventory produced by Atmel in the early stage. Atmel can certainly resume production of AT89C5 1 if the market needs it.
AT89S5 1/LS5 1 MCU is a low-power MCU with 4KB online course programming flash memory. It is compatible with the instruction system and pins of the general 80C5 1 series single chip microcomputer. On-chip flash memory can be reprogrammed online or programmed using nonvolatile memory. He integrated the general CPU and online programmable Flash on one chip, and formed a powerful, flexible and cost-effective microcontroller.
AT89S5 1/LS5 1 has the following characteristics:
-The on-chip program memory contains 4KB flash memory, allowing online programming, and the writing cycle can reach 1000 times;
-The on-chip data memory contains 128 bytes of RAM；;
-I/O port has 32 programmable I/O lines;
-with two 16 bit I/O lines;
The interrupt structure of the interrupt system has six interrupt sources, five terminal vectors and two interrupt priorities;
-The serial port is a full duplex serial communication port;
-with two data pointers DPTR0 and dptr1;
-Low power consumption and power saving modes include power saving mode and power off mode;
-including level 3 program lock bits;
The power supply voltage of -at89s 5 1 is 4.0-5.5V, and that of AT89LS5 1 is 2.7-4.0V；: ;
-oscillator frequency 0-33MHz(AT89S5 1), 0-16mhz (at89ls51);
-With on-chip watchdog timer;
-Flexible on-chip programming mode (byte and page programming mode);
-Plastic optical fiber; With power-off sign mode;
Compared with 89C5 1, the new functions of 89S5 1 include:
-Many new functions have been added, the performance has been greatly improved, and the price has remained basically unchanged, even lower than 89C5 1!
-ISP online programming function, the advantage of this function is that the chip does not need to be taken out of work when rewriting the program in the memory of single chip microcomputer.
Stripped in the environment. Is a powerful and easy-to-use function.
-The maximum operating frequency is 33MHz. As we all know, the limit working frequency of 89C5 1 is 24M, which means that S5 1 has more.
The working frequency is high, so it has faster calculation speed.
-UART serial channel with duplex.
-The watchdog timer is integrated internally, so it is no longer necessary to connect the watchdog timer unit circuit like 89C5 1.
-Dual data indicators.
-Power off sign.
-A brand-new encryption algorithm makes it impossible to decrypt 89S5 1, which greatly strengthens the confidentiality of the program. In this way,
We can effectively protect intellectual property rights from infringement.
-Compatibility: fully compatible with all series products of 5 1 For example, 805 1, 89C5 1 and so on.
Let the product. That is to say, all programs in textbooks and online tutorials (regardless of whether the single chip microcomputer used in textbooks is 805 1).
Whether it is 89C5 1 or MCS-5 1, etc. ), it can run as usual on 89S5 1, which is called backward compatibility.
Pin arrangement and function
AT89S5 1/LS has three packaging forms: PDIP, TQFP and PLCC. The pin arrangement of PDIP package is shown in the figure.
The pin functions are as follows:
-P0 port -8-bit open-drain bidirectional I/O port.
P0 port can be used as a general-purpose I/O port, but a pull resistor must be connected externally. As an output port, each pin sinks 8 TTL current. As input, first set the pin to 1.
The P0 port can also be used as the multiplexing line of the low-order eight-bit address/data bus of the external program memory and the data memory. In this mode, the P0 port contains an internal pull-up resistor.
When programming in Flash, Po port accepts code data; During program verification, P0 port outputs code byte data (external pull-up resistor is required).
-P 1 port -8-bit bidirectional I/O port with built-in wire pull resistor.
P 1 can be used as an ordinary I/O port. The output buffer can drive four TTL loads; When used as an input, the cross pin is set to 1 and raised to a high level by the on-chip pull-up resistor. The pin of P 1 port can be pulled down by external load, and the pull-up resistor provides pull-up current.
Parallelism in flash memory
During programming and verification, the P 1 port can enter a low byte address.
During serial programming and verification, P 1.0/MOSI, P 1.6/OSI and P 1.7/SCK are serial data input, output and shift pulse pins respectively.
8-bit bidirectional I/O with internal pull resistance.
When P2 port is used as the output port, it can drive four TTL loads. When used as an input port, first set the pin to 1 and raise it to a high level through an internal pull-up resistor. If the load is at a low level, the current is output through the internal pull-up resistor.
When the CPU accesses the external memory with the address of 16, the P2 port provides the upper 8-bit address. When CPU addresses external memory with 8-bit address, P2 port is the content of P2 special function register.
When programming and checking FLASH in parallel, P2 port can input high byte address and some control signals.
-P3 port-This office has an 8-bit bidirectional port with internal pull-up resistor.
When the P3 port is on the left and right, the output buffer can absorb the current of 4 TTLs. When used as an input port, manually set the pin to 1 and raise the internal pull-up resistor to a high level. If the external load is at a low level, the current is output through the internal pull-up resistor.
When programming and checking in parallel with FLASH, P3 port can input some control signals.
In addition to general I/O functions, P3 port has other functions, as shown in the following table:
pin
sign
explain
P3.0
receive data
Serial port input
P3. 1
TXD
Serial port output
P3.2
INT0
External interrupt 0
P3.3
INT 1
External interrupt 0
P3.4
T0
External counting input of T0 timer
P3.5
T 1
External counting input of T 1 timer
P3.6
Wassermann reaction
Write gating of external data memory
P3.7
road
Read gating of external data memory
-ale/Prog-data latch allows/programs the pulse signal terminal.
When CPU accesses external program memory or external data memory, ALE provides a data latch signal to lock the low 8-bit address in the spoofed data latch.
When programming in parallel with FLASH, this pin is also the input of programming negative pulse.
During normal operation, the pin port outputs pulses with rated frequency, which is 1/6 of the rated frequency, and can be used for external timing or other trigger signals. It should be noted that every time the CPU accesses the external data memory, it will lose an ALE pulse.
If necessary, ALE operation can be prohibited by setting bit 0 of SFR(8EH) to 1, but ALE is still valid when using MOVC or MOVX instructions. That is, the disable bit of ALE does not affect the access to external memory.
-psen- external program memory read strobe signal, active low.
When AT89S5 1/LS5 1 executes the instruction code from the external program memory, PSEN is valid twice every machine cycle. When accessing external data storage, it is invalid.
-ea/VPP- allowed by external program memory.
When EA is grounded, CPU only executes the program of external program memory; When the EA is connected to Vcc, the CPU first executes the program in the on-chip program memory (0000H ——0FFFH), and then automatically switches to execute the program in the off-chip program memory (1000h-ffffh).
If the program lock bit LB 1 is not programmed (p), the EA value will be latched on the chip at reset.
When programming in parallel with FLASH, this pin can participate in the programming voltage Vpp of 12V.
-Xtal 1 and XTAL2-Xtal 1 are the inputs of the on-chip oscillator inverting amplifier and the clock generator, and XTAL2 is the output of the on-chip oscillator inverting amplifier.
-rst- Reset input segment, active high.
When the oscillator works stably and effectively, the RST terminal remains high for two machine cycles, which resets the device. When the watchdog timer overflows the output terminal, this pin will output a high level for 98 oscillation periods.
-VCC-input terminal of power supply voltage.
-gnd ...-power ground.
Special function memory
Special function memory of AT89S5 1/LS5 1
serial number
address
sign
Reset value
explain
1
80H
P0 protein
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P0 port latch
2
8 1H
Special card
07H
stack pointer
three
82H
DP0L
00H
Data pointer DPTR0 low byte
four
83H
DPoH
00H
Data pointer DPTR0 high byte
five
84H
DP 1L
00H
Data pointer DPTR 1 low byte
six
85H
DP 1H
00H
Data pointer DPTR 1 high byte
seven
87H
PCON
0XXX0000B
Timer control timer
nine
89H
TMOD
00H
Timer mode register
10
8AH
TL0
00H
Timer 0 low byte
1 1
8BH
TL 1
00H
Timer 1 low byte
12
8CH
TH0
00H
Timer 0 high byte
13
8DH
TH 1
00H
Timer 1 high byte
14
8EH
AUXR
XXX00XX0B
Auxiliary register
15
90H
P 1
Familial benign hypercalcemia Familial Benign Hypercalcemia
P 1 latch
16
98H
SCON
00H
Serial port control register
17
99H
SBUF
XXXXXXXXB
Serial port data buffer
18
0AOH
P2
Familial benign hypercalcemia Familial Benign Hypercalcemia
P2 port latch
19
OA2H
AUXR 1
XXXX XXX0B
Auxiliary register 1
20
0A6H
WDTRST
XXXX XXXXB
WDT reset register
2 1
0A8H
Industrial Engineering (industrial engineering)
0XX00000B
Interrupt enable register
22
0BOH
P3
Familial benign hypercalcemia Familial Benign Hypercalcemia
P3 port latch
23
0B8H
Internet Protocol (internet protocol)
XX00000B
Interrupt priority register
24
0D0H
Graduate work visa
00H
The PacificSouthwest.
25
0E0H
Air Control Center (air control center)
scold
storage battery
26
0FOH
B
00H
Base address register
Power failure sign
POF is PCON.4 When the power is on, the POF is set to 1, and the POF bit can be set and cleared by software. Reset does not affect the POF bit value.
Terminal and interrupt register
AT89S5 1/LS5 1 contains six interrupt sources and five interrupt vectors (interrupt service program entry addresses), as shown in the following figure:
In the figure, the interrupt flags TF0 and TF 1 of Timer 0 and Timer1are set at S5P2 of each machine cycle (when overflowing), and then queried by the on-chip line in the next machine cycle.
No interrupt source can be enabled/disabled by setting or clearing a bit in the special function memory IE. IE contains an interrupt master bit EA, which can enable/disable all interrupts.
That is, your functions are as follows:
IE Address =A8H Reset Value = 0xx0000b
Addressable bit
MSB LSB
Bit address
AFH
AEH
Vascular vasopressin
Automated exchange
personal injury
Advanced Attack Helicopter (advanced attack helicopter)
A9H
A8H
Bit sign
Electronic arts game company
—
—
Salvador
ET 1
EX 1
ET0
EX0
1 in each position indicates that interrupts are allowed, and each bit is cleared to 0 to indicate that interrupts are disabled.
These include:
EA interrupt master control bit. EA=0, all interrupts are prohibited; EA= 1。 Whether each interrupt is allowed depends on the control bits of other interrupts.
ES serial port serial interrupt enable bit.
ET 1 timer 1 interrupt enable bit.
EX 1 external interrupt 1 interrupt enable bit.
ET0 Timer0 interrupt enable bit.
EX0 External Interrupt 0 Interrupt Enable Bit.