Understand the front end

The understanding front-end here refers to being familiar with Verilog hardware description language (no need to write code yourself). Of course, if you have written RTL code, many Daniel have done front-end design in practical work before. When you get a designed RTL, you need to know which functional sub-modules are included in the design and the clock circuit structure in the design, so as to write constraints later. Yes, you are absolutely right, that is, you need to be able to write binding documents yourself.

Familiar with synthesis

When RTL is ready, it can be used for logic synthesis. The synthesis mentioned here is not a simple operation process.

First of all, we need to communicate with front-end engineers to understand the design architecture, clock circuit structure, synchronous and asynchronous relationship between clocks, chip application scenarios and so on.

Second, according to the design requirements, start to write the design constraint document SDC, and ask the front-end design engineer to review it (this process requires constant communication with the front-end design engineer, especially when making a new design for the first time).

Thirdly, the scanning chain insertion method is formulated, the number of scanning chains is allocated, the test coverage is guaranteed, and the scanning test diagram is generated.

Fourthly, PPA optimization (performance, power consumption, area) is carried out in DC/DCT.