Kengteng Electronic Technology Co., Ltd. (Cadence Design Systems, Inc；; NASDAQ: CDNS is a software company specializing in electronic design automation (EDA), which was formed by the merger of SDA Systems and ECAD on 1988. Is the world's largest supplier of electronic design technology, programming services and design services. Its solution aims at upgrading and monitoring the design of semiconductors, computer systems, network engineering and telecommunications equipment, consumer electronics and other types of electronic products. Products cover the whole process of electronic design, including system-level design, functional verification, ic synthesis and layout, simulation, mixed-signal and RF IC design, fully customized integrated circuit design, IC physical verification, PCB design and hardware simulation modeling. Headquartered in San Jose, California, USA, it has sales offices, design and R&D centers around the world. In 20 16, Cadence was named "100 the best company to work for in the world" by Fortune magazine.

Company name: Kengteng Electronic Technology Co., Ltd. Foreign name: Cadence Design Systems Founded: 1988 Abbreviation: Cadence Company Profile, Domestic Survey, Design Platform, China Distributor, Training Content, Product Introduction, Bottom Software, Software Management Optimization, Unveiling, University Plan, briefly introduce Cadence Company's electronic design automation, provide design methodology services, and help customers optimize the design process. Provide design outsourcing services to help customers enter new market areas. Since 199 1 year, the company has been ranked first in the international EDA market. World-renowned semiconductor and electronic system companies all regard Cadence software as the standard of their global design. Cadence is headquartered in San Jose, California, USA, with sales offices, design and R&D centers around the world. Now it has 4,800 employees and its revenue in 2003 was about $6,543.8 billion. Overview of Cadence design software in China Cadence China now has more than 400 employees, two R&D centers in Beijing and Shanghai, and its sales network is all over the country. Cadence has successively established a high-speed system technology center and an enterprise service center in Shanghai to provide users with high-quality and effective professional design and outsourcing services. Cadence Beijing R&D Center mainly undertakes the research and development of EDA software with American headquarters, and is committed to providing users with more perfect design tools and full-process services. In 2003, Cadence invested US$ 50 million to set up Zhongguancun -Cadence Software College in Beijing, aiming at training more senior designers of integrated circuits and electronic systems for China electronics industry. Design platform Cadence Allegro system interconnection platform can cooperatively design high-performance interconnection across integrated circuits, packages and PCB. By applying the collaborative design method of the platform, engineers can quickly optimize the system interconnection between I/O buffers and between integrated circuits, packages and PCB. This method can avoid hardware rework, reduce hardware cost and shorten design cycle. Constraint-driven Allegro process includes advanced functions of design capture, signal integrity and physical implementation. Because of the support of Cadence Encounter and Virtuoso platform, Allegro collaborative design method makes efficient design chain collaboration a reality. On June 17, 2008, Cadence announced their acquisition plan submitted to the board of directors of Mentor Graphics, that is, they bought Mentor Graphics in cash at the price of 16 USD per share, with a total transaction amount of1600 million USD. Cadence said that its cash purchase price was 30% higher than the common stock of Mentor Graphics at the close of June 16 (the last trading day of Cadence's public proposal). At the same time, it is 59% higher than the closing price of Mentor Graphics on May 2, when Cadence submitted its proposal to Mentor. This price is also 46% higher than the average closing price of Mentor Graphics in the past 30 trading days. In a letter to the board of directors of Mantu Company on June 7, 2007, Michael J. Fister, President and CEO of Cadence, recalled that he first talked about merging Cadence and Mantu Company on April 6, 2008. However, he expressed disappointment because Rheinland was unwilling to negotiate further. At the news and analyst meeting held on June 18, Fuerstl said: "Mentor Graphics told us that by the end of May, they all wanted to remain independent and did not want to discuss our acquisition plan further. Because they refused to negotiate with us, we decided to make our acquisition plan public. In a letter to Rhines, Fister explained the significance of this merger. He wrote: "We believe that the combination of Cadence and Mentor Graphics will provide customers with a broader and more comprehensive integrated product and technology portfolio, which can better solve the challenges that customers encounter when developing the next generation products. "Fuerstl added:" The combination of Cadence and Mentor Graphics can pool our innovative talents, thus providing more comprehensive cutting-edge solutions and providing customers with a new level of customer experience. Through joint efforts, we will speed up the innovation speed and efficiency of customers and better meet the needs of customers to develop new products. "Whether Cadence's proposal can be realized depends on whether a merger agreement acceptable to both parties can be reached. Mentor Company (headquartered in Wirseen, Oregon) has about 4,200 employees and earned about $850 million in the past 65,438+02 months. In 2007, the revenue of Cadence company was 16 1 billion USD. Recently, Cadence has participated in many acquisitions. For example, in March 2008, Cadence acquired Chip Estimate, a developer of IC planning and ip reuse management tools. In August 2007, Cadence acquired DFM technology developer Clear Shape Technologies. A month ago, it acquired Invarium, a professional lithography company. Fuerstl told a news and analyst conference: "In the past ten years, we have completed 36 different acquisitions, and these companies face the same challenges. We fully consider the needs of customers' solutions and show how to achieve the effectiveness of production. There are many factors, and we have to do it. In a very difficult period of customer environment, they are facing cost challenges, and merger is the best time. "China's after-service education distributor Recently, Cadence Company signed a distribution cooperation agreement with Ke Tong Group (code: COGO), the largest distributor of integrated circuit components in China, and authorized the latter to be its distributor in China. According to the agreement, Ke Tong Group will authorize the distribution of Cadence's OrCAD and Allegro products in China. Training content 1, Introduction to Allegro Teaching;

2. Basic operation and design process of Allegro

3. The setting of teaching environment for Allegro;

4. Introduction to the use of Orcadcis software.

5. Import design data;

6. Preliminary setting of design rules;

7. Location (Component Layout)

8. Share and introduce typesetting skills;

9. Introduction of filled wiring and operation training of embedded system.

10, dynamic filling;

1 1, screen printing processing;

12, assembly and processing;

13, adding test points (test points)

14, compilation of Gerber data;

15, Gerber data output;

Basic use of 16 and Cam350

17, checklist;

18, production file output;

19, panel drawing (imposition)

20, cardboard requirements to fill in;

2 1, introduction of high-speed circuit;

22. Introduction to the Use of Constraint Manager

23. Introduction and use of Polar software;

24. Introduction to PCBA;

25, Pcb factory process introduction

26. Introduction of manufacturable design;

27, the design of high frequency circuit;

28. Brief introduction of blind buried hole design;

29, EMI boating and countermeasures;

30. Introduction of electronic components;

3 1, packaging design1(dip);

32. Package Design 2(smt)

33.Pcb design management and organization;

34. skills introduction;

35. Course summary introduces 1, board-level circuit design system, including schematic diagram input, generation, analog digital/mixed circuit simulation, fpga design, pcb editing and automatic layout mcm circuit design, high-speed pcb layout design simulation, etc. Including: * Concept HDL schematic design input tool for NT and Unix products. * Check Plus HDL schematic design rule checking tool. (NT & UNIX) * PCB layout planning tool for SpectraQuest engineers (NT&; Unix) * Allegro Expert PCB layout editing tool (nt&; Unix) * Spectra Expert AutoRouter Expert PCB automatic routing tool * SigNoise signal-to-noise ratio analysis tool * EMControl electromagnetic compatibility checking tool * Synplify FPGA/CPLD comprehensive tool * HDL Analyst HDL Analyzer * Advanced MCM package designer's advanced package design tool 2 .Alta system-level wireless design. This product is mainly used in network. Personally, I think. In particular, it contains a set of gsm models, and it is easy to develop things like cdma. But I think it can also be used for signal processing and image processing, because the spw inside is so awesome, at least it seems that the best place of spw is the interface with hds and matlab. Many models in matlab can be directly transferred to spw, and then the simulation code in C language or hdl language can be generated by hds. I don't have a license for this. I haven't tried. Look at what the open book says. That is to say, if you do it simply, make a model directly with matlab, and then you can layout it, hehe. Alta mainly includes the following packages: * SPW (CIERTO signal processing system) signal processing system. It can be said that spw contains many functions of matlab, even a bit like demo, hehe. It is an environment for modular design, simulation and realization of electronic systems. Its common application fields include wireless and wired carrier communication, multimedia and network equipment. It is an ideal environment for algorithm design, filter design, C code generation, joint design of software and hardware structure and hardware synthesis. One of the most interesting is the signal calculator. * HDS (Hardware Design System) Hardware System Design System is one of the integrated components of SPW. Include simulation, library and analysis extensions. Spw can analyze behavior level and rtl level code generation at fixed points. * Mutimedia multimedia design kit I haven't seen this part. It looks interesting in the demonstration of product release. It is said that multimedia application environment can be generated quickly. It can be used to design multimedia applications, including video conference system, digital TV and any kind of image processing system. * Wireless (IS- 136 verification environment) radio technology standard system-level verification tool, which can generate, develop and improve the signal processing algorithm conforming to IS-54/ 136 standard on the system-level abstraction layer. After the hardware structure design is completed, hds can be used to directly generate a comprehensive hdl description and the corresponding standard test platform. * IS-95 wireless standard system-level verification * BONeS network design tool for analysis and verification. This thing looks interesting. It is a software system specially used for designing multimedia network structure and discussion. This thing looks interesting. It is a software system specially used for designing multimedia network structure and discussion. It can be used to quickly generate and analyze the abstract model of information flow between structural units and establish a complete wireless network operation model. For example, users can improve the algorithm of atm converter and establish its application model based on microprocessor, including cache and memory, bus and communication processing methods. * G, VCC virtual convergence design toolkit, used for system-level design environment based on reusable ip core. Among these things, I think it is very important to have the support of the library. For example, in spw, the final rtl level can only be achieved with the support of hdl libraries of different algorithms. In the university edition, there are no licenses for these components and some bin codes. Everyone should be familiar with the software designed by 3.LDV, because the D version of pc seems to be very popular. Here is a brief introduction to cadence's ldv process, although I feel that most people use synopsys. First, the boss puts forward an idea, and then the designer (student) describes the design in vhdl or verilog language and generates hdl code. Then we can use Verilog-XL, NC-Verilog, Leapfrog VHDL NC-VHDL and other tools to simulate the behavior, judge the feasibility of the design, verify the function of the module and debug the design. Then, in the debugging and analysis environment, the simulation results are analyzed by VeriSure/for Verilog (VHDL cover/for VHDL) to verify the test level. Then we use Ambit BuildGates for synthesis, use the synthesized delay estimation (SDF file) for gate-level simulation, and then use verifault for fault simulation. This is a very simple process. In fact, after system-level design, design simulation is needed, if large modules are designed. Moreover, when synthesizing, writing the comprehensive limit file is also very troublesome and needs to be repeated many times. The above process does not include adding tests (such as scanning). The above process is possible for small designs. LDV includes the following modules: * verilog-xl Emulator * Leapfrog vhdl Emulator supports the simulation of mixed languages, and accelerates the simulation of vhdl language through post-compilation simulation. * Affirma NC Verilog simulator is mainly characterized by being suitable for large-scale system simulation. * Affirma NC VHDL simulator is suitable for VHDL language simulation. * Affirema formal verification tool-equivalence checker * Verifault-XL fault simulator feels that fault simulation is the most time-consuming simulation step. Used for testability design of test chips. * VeriSure code coverage checking tool * Envia BuildGates comprehensive tool Among the features of Ambit BuildGates, I think its PKS feature should be the best. Of course, I don't have its license. Because in pks characteristics, ambit can call physical layout tools such as pdp of se to estimate the delay. In this case, I think its timing is better than synopsys. In the small design of synopsys I tried, the error is about 100%, hehe. The comprehensive time is 2.9ns and the layout optimization time is 5ns. But the synthesis of ambit is definitely worse than synopsys, because it has no large library support, and I think it can be clearly felt when synthesizing large logical blocks. I haven't tried it. That prawn has time to compare their comprehensive characteristics. 4. Deep submicron design driven by time sequence. This part is the underlying design software. I feel that the work of the bottom design is a delicate work, and many repetitive processes are needed to go back and forth. In the previous design process (.6um and above), generally speaking, the connection delay can be ignored, or they have little influence on the design. After the design is completed, do pex and then simulate. If the design is small, it will probably pass. Many softwares directly consider the line delay in the layout stage, which is also the requirement of deep submicron design. Because the connection delay has a great influence on the overall design, even in the synthesis stage, the influence of layout planning needs to be considered. Synopsys and ambit and jupiter (two generations of love! The company's comprehensive software) and so on have added such considerations in their comprehensive process. In candence's software, there are mainly two softwares, SE and design planner, which are used for timing-driven design. Cadence's software was launched long ago, but the update was slow. For example, Avanti's software unifies almost a whole set of processes, such as layout, time series analysis and synthesis. Cadence has no innovation at the bottom, just like it did a few years ago. 5. Fully customized ic design tool * Virtuoso schematic synthesizer: Introduction to ic design. It is a schematic input method that can be mixed. Support text input in vhdl/hdl language. * Affirma simulation design environment This is a good mixed-signal design environment * Virtuoso Layout Editor Layout editing It supports parameterized units, which should be a good feature. * Affirma Spectra advanced circuit emulator and hspice emulator. * Virtuoso layout synthesizer's direct layout generation tool, small-scale design environment * Assura verification environment, including diva * dracula verification and parameter extraction package * ICCragtsman layout design environment. More suitable for ip-oriented design. The underlying software Cadence has the following underlying software: Logical design planner, which is a planning tool for early design. Its main purpose is to predict the time delay and generate the line load model for the synthesis tool. This tool is used to provide physical information of design for logic designers in the early stage of physical design. Physical Design Planner: Pre-planning of physical design. For large-scale design, the pre-planning of physical design is very important. In many processes, it is necessary to verify the design sequence after the previous layout is completed. * se (Silicon Ensemble) Layout Router se is a platform for layout, which can provide interfaces for multiple layouts and post-processing software. * PBO optimization layout-based optimization tool * CT-GEN clock tree generation tool * RC parameter extraction HyperRules rule generation, super-extraction RC extraction, RC simplification, delay calculation * Pearl static time series analysis In addition to friendly interface, Pearl can also exchange data with spice simulator to simulate critical paths. * Software Management Optimization of Vampire Verification Tool In order to better manage and dispatch the license issuance of genuine software, Lanman Technology Company has spent five years in software license monitoring management and accumulated profound technical experience in the field of license control. LMTLicManager software centralized monitoring and management system developed by LMTLICManager can provide comprehensive and specific functions such as license data statistical report, license usage analysis, automatic license recovery and release, license grouping scheduling, license lending and license priority authorization. Its solution has been adopted by many Fortune 500 enterprises, which can save more than 30% of the license fees for enterprises. Cadence Design Systems (NASDAQ: CDNS), the global leader in electronic design innovation, introduced a new implementation method of integrated chips, which pushed the chip development from the point-of-use tool repair method to a simplified end-to-end method of integrated technologies, tools and methods. Compared with the cautious and compartmentalized method traditionally adopted by semiconductor and system enterprises to realize silicon realization, this method is a major breakthrough. The term "silicon realization" refers to all the steps needed to transform the design into a silicon chip, which is an important part of EDA360 action. Cadence-Ampreg, a new method, focuses on providing products and technologies that meet the requirements of unified design intent, design extraction and design convergence, so as to obtain a decisive way to realize silicon. The biggest technical and commercial challenges faced by chip and system manufacturers are: mixed signal, low power consumption, billion gates/billion hertz, verification, SiP and collaborative design, overall efficiency and indicators. Designs that meet the above three requirements can bring obvious and quantifiable efficiency, predictability and profitability to these manufacturers. With the introduction of new technologies into the whole company's silicon realization product portfolio, cadence &; Reg is a big step forward to ensure that It and upcoming products meet these three key requirements and can be integrated into the whole process. Intentionally, the new features enable analog, physical and electrical constraints to drive digital content into mixed signal streams and vice versa. In terms of extraction, the design team can create a bare chip abstraction for system-level packaging and three-dimensional IC design. For design integration, Cadence establishes a new physical, electrical and functional relationship between logic design, verification and implementation, thus providing better integration in the design process and shortening the ECO cycle. For more details, you can download the white paper on chip implementation here. "This is the best way I have ever seen for Cadence," said gary smith, chief analyst of EDA. "Cadence constantly clarifies its strategy, introduces talents, and links talent performance with EDA360 strategic goals. The purpose of this is to break the situation of single-handedness and let all departments of the company work together. They are trying to achieve many things that other EDA companies have tried but failed. " "Under the current complicated design and market pressure, chip development enterprises urgently need to make significant improvements in efficiency and profitability, but it is impossible to achieve this goal just by piecing together a large number of tools from different companies," said Xu Jiping, senior vice president in charge of research and development of Cadence Silicon Realization Products Group. "Our R&D team has been committed to building tools that can meet the requirements of unified design intent, design extraction and design integration, and our products released in the future will continue to meet these core elements. Finally, we hope to provide many seamless and end-to-end design processes, and their inherent high efficiency will bring obvious market advantages to customers. " University Plan It is reported that cadence, the world's largest EDA software provider, is actively cooperating with some famous universities of science and engineering in China and actively promoting its university plan by setting up joint laboratories. Universities that have reached cooperation agreements include Beijing University of Technology, Suzhou University and South China University of Technology. (The picture below shows Xiong Wen, manager of cadence China, Wang Qiping, product manager of cadence of Ke Tong Group, and most leaders of South China University of Technology and Jiangsu attended the unveiling ceremony of the joint laboratory). South China University of Technology -Cadence Joint Laboratory Cadence Company (Chinese name is "Kengteng Electronics" or "Yihua Computer") is a leading EDA (Electronic Design Automation) tool software company in the world, headquartered in California, USA. Its complete product chain can serve all aspects of the electronics industry and provide full-process tool support from IC design to PCB design. Worldwide, the market share is far ahead of other competitors. A large number of star enterprises in the electronics industry, such as Apple, Samsung, Hewlett-Packard, Dell, Ericsson and Huawei. , is cadence's client.

Cadence has a high brand influence and market share in the world, while China, a big electronics manufacturing country, is moving from China manufacturing to China design, and the potential of China market is valued by more and more international multinational companies. Cadence's cooperation with universities conforms to the trend of China's design development, devotes itself to cultivating future design talents, and at the same time makes up for the shortcomings of the early education market!

In the education market, the choice of EDA tools is usually preconceived. Students' learning experience in choosing tools at school will have an important influence on which tools they choose to use when they enter the work. In the previous education market in China, Cadence company obviously didn't arrive first, but was occupied by another EDA company. Although we lost the opportunity in the domestic university plan, we can also take advantage of the leading products and work with some high-level universities in China to find a way to differentiate ourselves from other companies. Cadence has its own unique advantages for some high-end designs such as high-speed and high-density boards. The more high-end and complex design requirements, the more its products can show its characteristics. Therefore, by cooperating with some universities with strong scientific research strength in China and completing some high-level scientific research projects, cadence is expected to exercise the priority of "teaching mother tongue" in the field of high-end design. Thus paving the way for the growth and outbreak of the high-end market in the later period. It must be mentioned that Cadence's choice of Ke Tong Group as its partner is an expected move in its market strategy. Ke Tong Group is the largest distributor of parts and components in China, and also a listed company on NASDAQ. Not only does its online and offline business have huge customer resources, but its online business "Ketong Core City" has also become the most influential IC component e-commerce brand in China in just two years. Cadence chose Ke Tong because of the powerful online and offline three-dimensional service capabilities of Ke Tong. At the same time, Cadence's university project is also actively promoted by Ke Tong Group.