Digital frequency meter is one of the important measuring tools in the field of modern electronic technology, and it is also widely used in many other fields. The digital frequency meter records the number of pulses measured in a specified reference time, converts them into frequencies and displays them in digital form. Digital frequency meter is used to measure the frequency of signals (square wave, sine wave or other periodic signals) and display them in decimal digits. It has the advantages of high precision, fast measurement speed, intuitive reading and convenient use.
An example of using VHDL language is as follows:
-Project Name: Constant Precision Frequency Meter
-target device: FPGA or CPLD.
-Revision 0.0 1-File created.
-Remarks: clk-System working clock, 2MHz.
-System reset signal, active at high level.
-FX is the signal to be tested.
Frequency nx is the count value of the signal to be measured.
-freqns is the count value of the standard signal.
-freq is the frequency of the signal to be measured.
-
-
Library IEEE
Use IEEE. STD_LOGIC_ 1 164。 All;
Use IEEE. STD_LOGIC_ARITH。 All;
Use IEEE. STD_LOGIC_UNSIGNED all;
-
The physical frequency meter is
Generic(clk_freq: integer: = 2000000); -System operating clock frequency
port(clk:in STD _ LOGIC；
Reset: in STD_LOGIC;
Fx: in STD_LOGIC; -The signal to be measured
freq ns:out natural；
freq NX:out natural)；
-Freq:out natural)；
Terminal frequency meter;
-
The structural behavior of the frequency meter is
-
Signal Start: STD _ LOGIC- When the signal is high, the counter starts counting.
Signal CTRL:STD _ LOGIC；; -CTRL signal is a counter start signal generated by the signal to be tested and the strobe signal.
Signal CNTx: natural; -Signal counter under test
Signal CNT: natural; -Standard signal counter
-
begin
- *************************************** -
-Generate a strobe signal, which is active at high level.
GateCtrl : process(clk)
-
Variable CNT0: integer range 0 to 2 _ 097 _152; Gated signal counter
-
begin
If the rising edge (clk), then
If reset=' 1', then
CNT 0:= 0；
other
CNT 0:= CNT 0+ 1；
End if;
-
If reset=' 1', then
Start & lt= '0';
Elsif CNT0 & lt(clk_freq*3/4) Then
Go<=' 1';
other
Start & lt= '0';
End if;
End if;
End process GateCtrl
- *************************************** -
-generating a CTRL signal, and a counter start signal generated by the measured signal and the strobe signal.
CtrlGen: process (Fx)
begin
If the rising edge (Fx), then
If reset=' 1', then
CTRL & lt= '0';
other
CTRL & lt= start;
End if;
End if;
End process CtrlGen
- *************************************** -
Two counters are used to count the standard signal clk and the signal to be measured respectively.
-
-Count standard signal, which is valid during the high level of CTRL.
Counting: process (clock)
begin
If the rising edge (clk), then
If reset=' 1', then
CNTs & lt= 0;
Elsif CTRL=' 1' and then
CNTs & lt= CNTs+ 1；
other
CNTs & lt= 0;
End if;
End if;
End process count;
-
-The counting signal to be measured, which is valid during the high level of CTRL.
CountX: process (Fx)
begin
If the rising edge (Fx), then
If reset=' 1', then
CNTx & lt= 0;
Elsif CTRL=' 1' and then
CNTx & lt= CNTx+ 1；
other
CNTx & lt= 0;
End if;
End if;
End process CountX
- *************************************** -
The falling edge of-CTRL will output technical results and measured values.
Count: process (CTRL)
begin
If the falling edge (CTRL), then
If reset=' 1', then
FreqNs & lt= 0;
FreqNx & lt= 0;
-Freq & lt； = 0;
other
FreqNs & lt= CNTs
FreqNx & lt= CNTx
-Freq & lt； =(clk _ freq/CNTs * CNTx)；
End if;
End if;
End process count;
End the behavior;
The following is a test platform for the above modules, which has passed the simulation under Modelsim. Because of the large amount of data, it is recommended not to use Altera and ISE for simulation.
-
Library ieee
Use IEEE.std _ logic _1164. All;
Use IEEE.std _ logic _ unsigned.all;
Use ieee.numeric_std. All;
Entity tb is
End TB;
The architectural behavior of tb is
-Component Statement (UUT) of the device under test
Component frequency meter
Port (
Clk: in std_logic;
Reset: in std_logic;
Fx: in std_logic;
freq ns:OUT natural；
freq NX:OUT natural；
Frequency: beyond nature
);
End assembly;
-Input
Signal clk: STD _ logic: =' 0';
Signal reset: STD _ logic: ='1';
Signal FX: STD _ logic: =' 0';
-Output
Signal frequency: natural;
Signal FreqNx: natural;
-Signal frequency: natural;
-clock cycle definition
Constant clk_period: time: = 500ns
begin
-instantiate the unit under test (UUT)
Uut: frequency meter port mapping (
clk = & gtclk，
Reset => reset,
Fx => foreign exchange,
FreqNs = > frequency,
FreqNx = & gtFreqNx，
-Freq = > frequency
);
-Clock flow definition
Clk_process: process
begin
clk & lt= '0';
Wait for clk _ period/2;
clk & lt= ' 1';
Wait for clk _ period/2;
End the process;
-generating a signal to be measured
Fx_process: process
begin
Fx & lt= '0';
Wait for 2 * clk _ period
Fx & lt= ' 1';
Wait for 2 * clk _ period
End the process;
Stimulation process
Process process
begin
-Keep the reset state 100 milliseconds.
Wait for clk _ period *10;
Reset & lt= '0';
-Insert the stimulus here
Wait;
End the process;
End;
Reference principle M/T frequency measurement method.