Basic principle of charge pump phase-locked loop
The charge pump phase-locked loop (CPPLL) consists of a frequency and phase detector (PFD), a charge pump (CP), a loop filter (LF) and a voltage-controlled oscillator (VCO) [1 ~ 2], and its structural block diagram is shown in figure 1.
Phase-locked loop is a feedback system. By comparing the phase difference between the input signal and the feedback signal through a phase detector, an error current which is approximately linear with the phase difference is obtained. After the error current is integrated by the loop filter, an error voltage is obtained to control the output frequency of the VCO, thus locking the PLL. The charge pump consists of two switching current sources that drive capacitors. Charge pump PLL has two outstanding advantages: (1) the capture range is only determined by the output frequency of VCO; (2) If the mismatch and deviation are ignored, the static phase error is zero.
Main technical indexes of PLL
phase noise
Phase-locked loop is a circuit that processes phase signals, so it is easily affected by phase noise (in time domain, it corresponds to clock jitter). The main sources of phase noise are reference crystal oscillator, frequency divider, frequency discriminator and voltage controlled oscillator [3]. In-band phase noise is mainly determined by reference crystal oscillator, frequency divider and phase detector; Out-of-band phase noise is mainly determined by voltage controlled oscillator. That is to say, the phase-locked loop shows low-pass characteristics to the noise of reference crystal oscillator, frequency divider and phase detector; The noise of VCO presents Qualcomm characteristics. The phase noise can be reduced by increasing the phase detection frequency and reducing the loop bandwidth. The phase noise can be estimated by the formula (1).
=++( 1)
Where 1HzPN is the normalized noise floor of 1Hz and PFDF is the phase discrimination frequency.
Lost livestock
Stray is caused by nonlinearity of devices and microwave radiation. The main stray in PLL is reference stray, which is caused by mismatch between source current and sink current of charge pump, leakage of charge pump and insufficient power decoupling. When the phase detection frequency is low, the stray caused by charge pump leakage is dominant; When the phase detection frequency is high, the stray caused by the mismatch between the source current and the sink current of the charge pump is dominant. Generally speaking, the limit of high and low phase detection frequency is about 100 kHz ~ 200 kHz. The following measures can be taken to improve the spurious suppression: (1) avoid or use the mixer as little as possible, (2) add metal isolation at the mixer, and (3) have a good grounding.
stability
When external interference enters the circuit, the phase error of PLL will deviate from the original equilibrium state. When the interference disappears, such a phase-locked loop is stable if the loop can be restored to its original equilibrium state. Phase margin is often used to measure the stability of loop in engineering. The greater the phase margin, the more stable the loop is, but the greater the phase margin, the longer the transition process of the system response. Generally speaking, the phase margin is set between 45 and 55, and the loop bandwidth is set between110 and 1/20 of the phase detection frequency. In this way, PLL is easy to lock and the loop is stable.
Circuit realization
The 1.42GHz point frequency source designed in this paper provides local oscillator for superheterodyne receiver, and its principle block diagram is shown in Figure 2 [4 ~ 5].
The PCB material is RO4003C from ROGERS. The dielectric constant of the board is 3.38, the loss tangent is 0.0027, and the thickness is 0.508 mm ... The PCB is very thin, which can reduce the circuit size.
The chip used in the 2 0 MHz crystal oscillator is CFPT-9007, which has the characteristics of high stability and low phase noise. The phase noise of the crystal oscillator is-135dBc/Hz@ 1kHz, and its contribution theory to the system phase noise is as follows:
The phase detector chip adopts the ADF4 106 chip of analog devices, which integrates a frequency divider, a digital phase detector and a charge pump, and has a wide working bandwidth (0 ~ 6 GHz), low phase noise and a wide working temperature range. The normalized phase noise floor of ADF4 106 is about -2 19dBc/Hz, and the phase noise contribution of frequency discriminator/phase discriminator to the system can be calculated as-1 09dbc/Hz by equation (1). It can be seen that the phase noise of the whole PLL circuit is close to -98dBc/Hz@ 1kHz theoretically.
The VCO is V585ME48-LF from Z-Communications company. The frequency range of VCO is 950mhz ~ 2050mhz, the power supply voltage is 10V, the voltage control sensitivity is 8 1MHz/V, the phase noise is -99BC/Hz @ 10khz, and the output power is 2dBm. When the output frequency is 1.42GHz, the required tuning voltage is about +5V, so the power supply voltage of the charge pump of ADF4 106 is+5.5v. ..
Loop filter is a part that designers can design flexibly when designing PLL circuit. The function of loop filtering is to filter out the high frequency components and noise in the error voltage, so as to ensure the required performance of the loop and increase the stability of the system. This design adopts third-order passive filtering, as shown in Figure 3.
The resistance and capacitance values in the loop filter can be calculated manually. In order to simplify the design process, ADIsimPLL, a software of AD company, is used for calculation. Input the required parameters in the software interface, and the component value will be automatically calculated. After adjusting the loop bandwidth and phase margin properly, the PLL circuit will lock.
Microcontrol unit (MCU) adopts PIC 16F648A single chip microcomputer. The working voltage is +5V, the speed is up to 20MHz, and it has two 8-bit ports. Connected with ADF4 106, it sends data to the phase detector chip after power-on, and controls the R counter, N counter and functional latch inside the phase detector chip to lock the phase locked loop.
The output signal of voltage controlled oscillator must be adjusted by π attenuator and amplifier to meet the system requirements. Finally, it uses a filter to suppress spurs and make the spectrum more pure.
Electromagnetic compatibility considerations
In order to make a system have good performance, it is very important to consider electromagnetic compatibility. This design considers electromagnetic compatibility from the following aspects.
In order to match well, the characteristic impedance of signal line is 50 Ω when drawing PCB layout, and its width is 1.05mm after ADS calculation. Signal lines and chip pins are connected by gradient microstrip lines, which can reduce signal reflection. The power supply is connected from the outside through the through capacitor, which can prevent external interference signals from entering the circuit. In order to ensure good grounding when drawing the grounding pad, try to make the via close to the pad. The laying of floor is very important, and good grounding can effectively reduce stray, so it should be laid in the spare part of PCB board. The distance from the floor to the signal line is more than twice the thickness of PCB, that is, more than 1.0 16mm, which has little influence on the characteristic impedance of the signal line. The edges of the floor are evenly punched, and the spacing between vias is less than λg/20(λg is the wavelength in the medium corresponding to the maximum frequency of the system signal), and holes are randomly punched in the middle of the floor. This not only has good electromagnetic compatibility, but also increases the mechanical strength of PCB.
test result
The manufactured object is shown in Figure 4, with compact structure, small volume and good performance.
The power, phase noise and stray of frequency source are measured by Agilent E4407B spectrometer, and the results are shown in Figure 5.
conclusion
In this paper, the design method of L-band frequency source based on PLL is given, and the physical object is made, which proves the feasibility of the scheme. Through repeated debugging of the circuit, the performance is optimized. After measurement, the phase noise is -80.4dBc/ Hz@ 1kHz, the spurious suppression is better than -55dBc, and the output power is greater than 6dBm, all of which meet the requirements of the index. In addition, the circuit has simple structure, compact size and excellent performance, and can be used in practical circuits to provide local oscillator for receivers.
References:
Behzad razavi. Radio frequency microelectronics [M]. Beijing: Tsinghua University Publishing House, 2006.
Zhang Juesheng, Cao Lina. Phase lock and frequency synthesis technology [M]. Chengdu: University of Electronic Science and Technology of China Press, 1995
[3]ADI PLL FAQ [EB/OL].2003
Lu Jibing, Yang Tao. Design of X-band point frequency source and S-band transceiver unit [D]. Master's degree thesis of University of Electronic Science and Technology of China, 20 1 1
Chen, Chen, et al. Development of X-band frequency source based on PLL technology [J].Acta Microwave, 20 10, (8): 31-313