JTAG (Joint Test Action Group) Joint Test Working Group. It is a standard test protocol, which is mainly used for internal testing of chips. It is compatible with IEEE1149.1protocol, and many advanced chips have this protocol, such as FPGA and DSP.
JTAG port was originally only used to test the inside of the chip. Its principle is to define a test access port called TAP (test access port) inside the equipment, and then use special tools to test the inside. Now, all the components in the chip can be programmed and controlled through JTAG.
Let's introduce the interface definition of JTAG port!
There are many packages in JTAG port, such as 10 pin, 14 pin and 20 pin. Although the number and order of pins are different, they are all the same!
In the IEEE 1 149.5438+0 standard, the following requirements are mandatory:
1, TCK (test clock input) -JTAG port clock pin
The test clock input pin provides an independent basic clock signal for TAP operation, and all TAP operations are driven by this clock signal.
2.TMS (test mode selection input)-test mode selection input pin.
TMS signal can control TAP to switch between different states, which is effective at the rising edge of TCK.
3.TDI (Test Data Input)-Test Data Input Pin
TDI is a serial input interface for inputting all data into a specific register.
4.TDO (test data output)-Test data output pin.
TDO is an interface for serially outputting all data output from a specific register.
5.(VTREF)-Interface signal level
The interface signal level can be used to determine the logic level used by the JTAG interface of ARM.
Optional requirements in IEEE1149.1standard are as follows:
1, TRST (test reset input)-test reset input pin.
TRST signal can perform the same function as TMS, that is, it is used to reset (initialize) TAPController.
2.RTCK (Return test clock)-Feedback test clock.
This pin is used to synchronize TCK signals. When the clock signal fed back to the simulator by the target terminal is not used, it is directly grounded.
3.nSRST (system reset)-feedback pin of clock reset signal.
This pin can detect the reset of the target system or connect the system reset signal on the target board to directly reset the target system. It is suggested to add an appropriate pull-up resistor at the target end to prevent false triggering.
4. User-defined input
This pin can be connected to an IO of the target machine and be controlled by the upper computer.
5. User Output-User-defined output.
This pin can be connected to an IO of the target machine to feed back the status to the upper computer.
In fact, these optional pins are generally not used. In practical application, the appearance of 20-wire equal port is mainly to increase the ground wire and reduce the interference of JTAG.