Familiar with Verilog, c, Modelsim, ise 13. 1, NC, tcl.

Familiar with the front-end design and simulation of verilog digital circuit, including functional simulation and timing simulation.

Familiar with the development process of using FPGA based on xilinx, including IP core reconstruction of signal coding and decoding.

Familiar with the application of C and matlab to model and simulate the algorithm, and have a certain understanding of wireless communication processing algorithm.

Familiar with using TCL to write do files for modelsim and call batch simulation.

Exquisite word version of the resume template can click on my avatar to enter my library homepage;

Using desktop computer can better show the design effect of resume;

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