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Verilog reading frequency program
counter

For example, stop when the 50MHz clock reaches 50, and then read the counter at another clock.

Comparing the values of two counters, we can get the frequency relationship between them. For example, the other counter is 100, which is 100Mhz.

This is just a principle, but in actual processing, we should pay attention to the release of reset signal, the phase relationship between two clocks, the processing across clock domains and the delay. Doing it well will reduce the error.