MMU is the abbreviation of memory management unit, and its Chinese name is memory management unit. MMU is the control line used in the central processing unit (CPU) to manage virtual memory and physical memory. It is also responsible for mapping virtual addresses to physical addresses, providing memory access authorization for hardware mechanisms, and multi-user and multi-process operating systems.

TLB (Translation Reserve Buffer) is a cache used by the memory management unit to improve the conversion speed from virtual address to physical address.

TLB is a small virtual addressing cache, in which each row holds a block composed of a single PTE. If there is no TLB, you need to access the memory twice every time you fetch data, that is, look up the page table to get the physical address to fetch data.