The waveform simulation of VHDL frequency division program I wrote shows that the clock duty ratio is close to 33%, not 50%. Why is this so

I think your program can be written better, but it is not enough to add such a condition to this program.

Library? ieee？

Use? IEEE . STD _ logic _ 1 164 . all； ?

Use? IEEE . STD _ logic _ unsigned . all； ?

Use? IEEE . STD _ logic _ arith . all； ?

Entity? div？ Is it?

Generic (n: integer? := 10); ?

Port (clk:in? std _ logic？

clk_out:out？ STD _ logic)； ?

End? ; ?

Architecture? bh？ Yes? div？ Is it?

Signal? clk _ temp:STD _ logic； ?

Signal? Counter: Integer? Range? 0? Where to? n- 1； ?

Start?

clk _ out & lt=clk_temp？

Process (clk)?

Start?

if(clk'event？ And then what? So clk=' 1'?

If(counter=n- 1) then?

clk _ temp & lt=' 1'; ?

Counter < = counter+1; ?

elsif(counter & lt； N/2) So?

clk _ temp & lt='0'; ?

Counter < = counter+1; ?

elsif(counter & lt； N- 1) and then what?

clk _ temp & lt=' 1'; ?

Counter < = counter+1; ?

Or what? Counter < = 0;

End? If; ?

End? Process; ?

End? BH；