Source: Microelectronic packaging technology
With the rapid development of automobile electronic devices and other consumer electronic products, microelectronic packaging technology is facing challenges and opportunities brought by the development trend of "high cost performance, high reliability, multifunction, miniaturization and low cost" of electronic products. QFP (Quadrant Flat Package) and TQFP (Plastic Quadrant Flat Package), as the mainstream packaging forms of surface mount technology (SMT), have always been favored by the industry. However, when they package, mount and solder more VLSI with I/O pins under the limit of 0.3mm pin spacing, they encounter insurmountable difficulties, especially in the case of mass production, the yield will drop greatly. Therefore, BGA (ball grid array) with I/O of area array and spherical bump came into being, and then developed into chipscalpackage(CSP) technology. Using new CSP technology can ensure VLSI to achieve the smallest package size (close to the bare chip size) under the premise of high performance and high reliability, but the relative cost is lower, so it conforms to the development trend of miniaturization of electronic products and is a highly competitive high-density packaging form in the market.
The appearance of CSP technology is the development of advanced packaging technology based on die mounting, such as multi-chip module (MCM) and direct chip mounting (DCA), which injects new vitality and broadens the research and development ideas of high performance and high density packaging. When MCM technology is faced with the problems that bare chips are difficult to store, transport, test and age, CSP technology makes this high-density packaging design surface.
Characteristics and classification of 2CSP technology
2. Characteristics of1CSP
According to the definition of J-STD-0 12 standard, CSP refers to an advanced packaging form whose package size is not more than 1.2 times that of bare chip [1]. CSP is actually formed in the process of miniaturization of original chip packaging technology, especially BGA. Some people call it μBGA (micro-ball grid array, now only classified as a form of CSP), so it naturally has many advantages of BGA packaging technology.
(1) has a small package size, which can meet the requirements of high-density packaging. CSP is one of the smallest VLSI packages at present. See table 1[2] for the comparison between CSP package with the same pin count (I/O) and QFP and BGA package.
From the table 1, it can be seen that CSP with many package pins is much smaller than the traditional packaging form, and it is easy to realize high-density packaging. With the continuous expansion of the scale of integrated circuits, the competitive advantage is very obvious, which has attracted the attention of integrated circuit manufacturing industry.
Generally, the package area of CSP is smaller than110 of QFP with a spacing of 0.5mm, only1/3 ~110 of BGA [3]. Among all kinds of chip packages with the same size, CSP can accommodate the largest number of pins, which is suitable for multi-pin packaging and can even be applied to high-performance chips with I/O numbers exceeding 2000. For example, a QFP with a pin pitch of 0.5 mm and a package size of 40×40 has a maximum of 304 pins. To increase the number of pins, the pin spacing can only be reduced, but it is difficult for QFP to break through the technical limit of 0.3mm under the traditional process conditions. Compared with CSP, BGA package has 600~ 1000 pins, but it is worth noting that CSP is much easier to assemble than BGA under the same number of pins.
(2) The internal wiring length of CSP with excellent electrical performance (only 0.8~ 1.0mm) is much shorter than that of QFP or BGA [4], and the parasitic lead capacitance (
(3) easy to test, screen and age. MCM technology is one of the most efficient and advanced high-density packages at present. Its core technology is to install bare chip, which has the advantages of no delay in internal chip packaging and greatly improved component packaging density, so the future market is promising. However, the problems of die testing, screening and aging have not been solved so far, and it is difficult to obtain qualified dies, resulting in quite low yield and high manufacturing cost [4]; CSP, on the other hand, can age, screen and test in all directions, which is convenient to operate and repair, and can obtain a real KGD chip. It is imperative to install CSP instead of bare chip at present.
(4) that CSP package with excellent heat dissipation performance is connecte with the PCB through the solder ball, and the heat generated when the chip works is easily conducted to the PCB and radiate due to the large contact area; In the traditional TSOP (Thin Small Profile Package) method, the chip is soldered to the pcb through pins, and the contact area between the solder joint and the PCB is small, so it is relatively difficult for the chip to dissipate heat to the PCB. The test results show that conduction heat dissipation can account for more than 80%.
At the same time, CSP chip is installed face down, which can dissipate heat from the back and has good heat dissipation effect. The thermal resistance of 10mm× 10mmCSP is 35℃/W, TSOP and QFP can reach 40℃/w, the thermal resistance of CSP can be reduced to 4.2, and QFP is 1 1.8[3].
(5) No need to fill in the package. In most CSP packages, bumps and thermoplastic glue have good elasticity, and will not generate stress because of the different thermal expansion coefficients of wafers and substrates, so there is no need for underfill, which saves filling time and cost, which is impossible for traditional SMT packages.
(6) Good compatibility between manufacturing process and equipment. CSP has good compatibility with existing SMT processes and basic equipment, and the pin spacing completely conforms to the currently used SMT standard (0.5~ 1mm). There is no need to design PCB specially, and the assembly is simple. Therefore, the existing semiconductor processing equipment and assembly technology can be used to organize production.
2.2 basic structure and classification of CSP
The structure of CSP is mainly composed of IC chip, interconnection layer, solder ball (or bump, solder post) and protective layer. Interconnect layer is the key component of CSP package, and the internal connection between chip and solder ball (or bump, solder post) is realized by means of automatic tape (TAB), wire bonding (WB) and flip chip (FC). The typical structure of CSP is shown in figure 1 [6].
At present, more than 50 IC manufacturers around the world produce CSP products with various structures. According to the current development of various manufacturers, CSP packaging can be divided into the following five categories [7,3]:
(1) Flexible Circuit Package The basic structure of CSP package developed by Tessera Company of the United States is shown in Figure 2. It is mainly composed of IC chip, carrier tape (flexible body), adhesive layer and bumps (copper/nickel). The carrier tape consists of polyimide and copper foil. Its main features are simple structure, high reliability and convenient installation, and it can be welded with the original TAB(TapeAutomatedBonding) equipment.
(2) Rigid Substrate Interposer Package This CSP package developed by Toshiba Corporation of Japan is actually a thin ceramic substrate package, and its basic structure is shown in Figure 3. It is mainly composed of chip, alumina (Al2O3) substrate, copper (Au) bump and resin. It is completed by three steps: flip-chip welding, resin filling and printing. Its packaging efficiency (the ratio of chip to substrate area) can reach 75%, which is 2.5 times that of TQFP of the same size.
(3) Lead frame CSP package The basic structure of this CSP package developed by Fujitsu Company of Japan is shown in Figure 4. Divided into Tape-LOC and MF-LOC.
In both forms, the chip is mounted on the lead frame, and the lead frame is used as an external pin, so it is not necessary to make solder bumps, and the chip can be interconnected with the outside. It is usually divided into two forms: tape locking and MF locking.
(4) Wafer-level package The wafer-level package developed by ChipScale Company is shown in Figure 5. After the previous process of the wafer is completed, the wafer is directly packaged by semiconductor process, and the peripheral interconnection is built by dicing grooves, and then it is cut and separated into individual devices. WLP mainly includes two key technologies, namely redistribution technology and bump manufacturing technology. It has the following characteristics: ① small parts equivalent to the size of bare mold (cut into blocks in the last process); (2) Processing cost per wafer (wafer cost rate synchronization cost); ③ High machining accuracy (due to the flatness and accuracy stability of the wafer).
(5) The CSP structure developed by CSP mitsubishi electric Company is shown in Figure 6. Mainly composed of IC chip, molded resin and bumps. The pads on the chip are interconnected with bumps through metal wiring on the chip, and the whole chip is cast on resin, leaving only external contacts. This structure can achieve a very high number of pins, which is conducive to improving the electrical performance of the chip, reducing the package size and improving the reliability, and can completely meet the high I/O requirements of memories, high-frequency devices and logic devices. At the same time, because there is no lead frame and bonding wire, the volume is particularly small, which improves the packaging efficiency.
In addition to the five types of packaging structures listed above, there are many packaging structures that meet the definition of CSP, such as μBGA, land array CSP and stacked CSP (a multi-chip three-dimensional package).
Prospect of 3CSP packaging technology
3. 1 Problems to be further studied and solved
Although CSP has many advantages, as a new packaging technology, there are inevitably some imperfections.
(1) Standardization Every company has its own development strategy, and any new technology will have the problem of insufficient standardization. Especially when different forms of CSP are integrated into mature products, standardization is a big obstacle [8]. For example, there are many CSP forms being developed for chips of different sizes, so the assembly manufacturers need different basic materials such as sockets and carriers to support them. Due to the variety of devices, the requirements for materials are diverse, and the technical flexibility is poor. In addition, the lack of unified reliability data is also a prominent problem. In order to gain market access for CSP, manufacturers must provide reliability data as soon as possible to formulate corresponding standards. CSP is in urgent need of standardization, and designers hope that the package has a unified specification, not a separate design. In order to achieve this goal, the external dimensions, electrical characteristic parameters and pin area of the device must be standardized, and the best effect can be achieved only by adopting global packaging standards [9].
(2) Reliability Reliability testing has become an important link in the design and manufacture of microelectronic products. CSP is often used to prepare VLSI chips, the repair cost is higher than that of low-end QFP, and the system reliability of CSP is more sensitive than that of traditional SMT packaging, so the reliability problem is very important. Although automotive and industrial electronic products have low requirements for packaging, reliability is a major problem if they are to adapt to harsh environments, such as working in high temperature and high humidity. In addition, with the application of new materials and new processes, the traditional reliability definition, standards and quality assurance system can not be fully applied to the development and manufacture of CSP, and new and systematic methods are needed to ensure the quality and reliability of CSP, such as reliability design, process control, accelerated test under special environment, reliability analysis and prediction, etc.
It can be said that an effective solution to the reliability problem will be the key to the success of CSP [10, 1 1].
(3) Cost and price are always one of the most sensitive factors affecting the market competitiveness of products (especially low-end products). Although in the long run, the cost of smaller, thinner and more cost-effective CSP packages will decrease more than other packages every year, it is still a great challenge to overcome this obstacle in the short term [10].
The price of CSP is relatively high at present. The availability of high-density optical board, the difficulty of testing hidden solder joints (with the help of X-ray machine), the unfamiliarity of repair technology, the size of production batch and the problems involving local modification all affect the system-level price of products, which is higher than that of conventional BGA devices or TSOP/TSSOP/SSOP/SSOP devices. However, with the development of technology and the improvement of equipment, the price will continue to decline. At present, many manufacturers are actively taking measures to reduce CSP prices to meet the growing market demand.
With the miniaturization of portable products, the improvement of OEM's assembly ability and the continuous decline of silicon wafer process cost, wafer-level CSP packaging is carried out on the wafer, so it has strong competitiveness in cost and is the most competitive CSP packaging form, and will eventually become the most cost-effective packaging.
In addition, there are a series of problems about how to match CSP, such as fine spacing, the development of multi-needle PWB microplate technology and equipment, and the general installation technology of CSP on the board [12], which are also urgent problems for CSP manufacturers to solve at present.
3.2 Future Development Trend of Photothermal Power Generation
The development trend of (1) technology to terminal product size will affect the portable product market and also promote the CSP market. In order to provide users with the highest performance and smallest size products, CSP is the best packaging form. In line with the trend of miniaturization of electronic products, ic manufacturers are committed to developing CSP products of 0.3mm or smaller, especially as many I/O numbers as possible. According to the prediction of American Semiconductor Industry Association, the minimum pitch of CSP at present is equivalent to BGA level (0.50mm) of 20 10, while the minimum pitch of CSP at 20 10 is equivalent to the current flip chip level (0.25mm).
Because the advantages of existing packaging forms are different, it is a fast and low-cost way to improve the performance of IC products to realize the complementary advantages of various packages and the effective integration of resources. For example, SMT, DCA, BGA and CSP package forms (such as EPOC technology) are included in the same PWB as required. At present, this hybrid technology is being paid attention to, and some foreign structures are studying it deeply.
Pursuing high cost performance is the driving force for the wide application of wafer-level CSP. In recent years, WLP packaging has been paid more and more attention by the industry because of its advantages of small parasitic parameters, high performance, smaller size (close to the size of the chip itself) and decreasing cost. WLP starts from wafer to device, and the whole process is completed together. The existing standard SMT equipment can be used to optimize the production plan and organization. Silicon processing technology and packaging test can be carried out on the silicon wafer production line without sending the silicon wafer to other places for packaging test; The test can be completed at one time before cutting CSP packaged products, which saves the test cost. In a word, WLP has become the mainstream of photothermal power generation in the future [13~ 15].
(2) Application field CSP packaging has many incomparable advantages compared with TSOP and BGA packaging, which represents the development direction of micro-packaging technology. On the one hand, CSP will continue to consolidate its application in memory (such as flash memory, SRAM and high-speed DRAM) and become the mainstream of high-performance memory packaging; On the other hand, it will gradually open up new application fields, especially in the fields of network, digital signal processor (DSP), mixed signal and radio frequency, application specific integrated circuit (ASIC), microcontroller, electronic display screen and so on. For example, driven by digital technology, portable product manufacturers are expanding the application of CSP in DSP. At present, the CSP packaged DSP products produced by TI Company in the United States have reached more than 90%.
In addition, the application of CSP in passive devices is also receiving attention. The research shows that the size of CSP package is greatly reduced and the reliability is obviously improved due to the reduction of the number of solder connections.
(3) The market predicts that the output of CSP technology is very small when it is just formed, and 1998 has just entered mass production. However, the development momentum in the past two years is not what it used to be. In 2002, the sales revenue reached US$ 6,543.8+0.95 billion, accounting for about 5% of the integrated circuit market. Foreign authoritative organization "ElectronicTrendPublications" predicts that the global market demand for CSP will reach 64.81100 million pieces in 2004, 88.71100 million pieces in 2005, and 10373 million pieces in 2006, and it is expected to increase to 65.438+026.50000080006