Structure and Programming of ARM Embedded System (2nd Edition) Directory Chapter 1 Introduction 1./definition of embedded system1./development of embedded system 1. 1 .2 definition and characteristics of embedded system/ .2.661.2.2 Naming Rules for Typical 438+0.2 ARM Kernel Version 2. 1.3 Core Series of Mainstream ARM Processor and Its Application 2.2ARM Kernel Module 2.3 Working Mode of ARM Processor 2.4 Internal Register 2.4. 1 General register and its allocation 2.4.2 program status register 2.5ARM exception handling 2.6 storage mode and memory mapping mechanism 2.7ARM pipeline technology analysis thinking and practice Chapter III ARM instruction set addressing mode 3. 1ARM instruction encoding format 3.2 data processing instruction unsigned byte addressing 3.3.3 halfword and signed byte addressing 3.4 batch loading/ Memory instruction addressing mode 3.5 Thinking and practice on coprocessor instruction addressing mode Chapter IV ARM instruction set system 4. 1 data processing instruction 4. 1 basic data processing instruction 4. 1.2 multiplication instruction 4. 1.3 miscellaneous data processing instruction 4.2ARM branch instruction 4.3 load/store instruction 4.3./. Store Word and Unsigned Byte Instruction Signed Byte Access Instruction 4.4 Batch Load/Store Instruction 4.4. 1 Basic Batch Word Data Load/Store Instruction 4.4.2 User Mode Batch Word Data Load/Store Instruction 4.4.3 Batch Word Data Load Instruction with PSR Operation 4.5 Exchange Instruction 4.6 Program Status Register PSR Access Instruction 4.7 Co-processor Operation Instruction 4.7./kloc-0 Coprocessor data operation instruction 4.7.2 coprocessor load/store instruction 4.7.3ARM register and coprocessor register data transmission instruction 4.8 Thinking and practice of abnormal generation instruction 5. 1.4 Thumb instruction with high register operation 5. 1.5 arithmetic operation instruction with SP/PC 5.2Thumb memory operation instruction 5.2./ Kloc-0/ byte, Half-word and word load/store instruction 5.2.2 Batch load/store instruction 5.3Thumb branch instruction 5.3. 1B branch instruction 5.3.2 Branch instruction with link 5.3.3 Branch instruction with state switch 5.4Thumb soft interrupt instruction 5.5Thumb instruction function code segment analysis 5.5. 1 Comparison of Thumb and ARM's Implementation Functions 5.5.2 Comparison of Thumb and ARM's Performance Thinking and Practice Chapter VI Assembly Pseudo-instruction and Pseudo-operation 6.65438+ According to the definition, Pseudo-operation 6.3.3 Assembly Code Control Pseudo-operation 6.3.4 Assembly Information Report Control Pseudo-operation 6.3.5 Instruction Set Type Identification Pseudo-operation 6.3.6 File contains Pseudo-operation 6.3.7 Other Pseudo-operations 6.4 GNU. Control Pseudo-operation 6.4.4 Pre-definition Control Pseudo-operation Thinking and Practice Chapter VII Assembly Language Programming 7. 1ARM assembly statement 7. 1. 1ARM assembly statement format 7. 1.2ARM assembly statement 7.2 assembly statement and compilation description 7 .2. 1 GNU environment ARM assembly statement format 7.2.2GNU environment ARM assembly program compilation 7.3ARM assembly language programming specification 7.4ARM assembly language programming example analysis thinking and practice Chapter 8 mixed programming of ARM assembly language and embedded C 8. 1 embedded C programming specification 8.2 Bit operation in embedded C programming. 8.3 Some Precautions for Embedded C Programming 8.3. 1 Variable Restriction 8.3.2 Address Forced Conversion and Use of Multilevel Pointers 8.3.3 Pretreatment 8.4 Embedded C Programming Format 8.5 Procedure Call Standards ATPCS and AAPCS 8.5. 1 Rules for the use of registers 8.5.2 Rules for the use of data stacks 8.5.3. Rules for parameter transfer 8.6.2 Mixed programming of ARM assembly language and embedded C 8.6. 1 embedded assembly 8.6.2 Thinking and practice of mutual calling between ARM assembly language and embedded C program Chapter 9 S3C44B0/S3C241S3C2444. Kloc-0/ Processor Introduction 9.2S3B0/S3C241S3C2440 Storage Controller 9.2 S3C24 10 Storage Control Register 9.2.6SDRAM Interface Circuit Design 9.2.7S3C44B0 Memory Initialization Example 9.3C24 10/ S3C2440 NAND flash controller 9.4S3C440B0/S3C241S3C2440 Clock power management 9.4.1S3C44B0/S3C2440 UART operation10./Kloc .4U art interrupt and baud rate calculation10.1.5S3C44B0/S3C241S3C2440UART special function register10.1.6S3C4B0/S3C24/kloc-. 0 UART design example 6544S3C2440 I2C bus function module 10.2.3S3C44B0/S3C2410/S3C2440I2C bus operation10.2.4S3C44B0/S3C2410. S3C24 10/S3C2440 I2C bus design example 1 0.3S3CC4B0/S3C2410/S3C2440 LCD controller 10.3. 1LCD introduction1 0.3s 3c 44 b 0s 3c 2440 LCD controller module10.3s3c44b0/s3c3c2410/s3c2440 encapsulation and I/O multiplexing information Appendix B link positioning and system boot program Appendix CARM embedded system structure course exam standard test questions reference.

(This catalogue is the second edition, updated on July 20 13)