The deposition methods of (1) thin films vary according to different uses, and the thickness is usually less than1μ m.. There are various films, such as insulating films, semiconductor films and metal films. The deposition methods of thin films mainly include CVD (Chemical Vapor Deposition) CVD) PVD (Physical Vapor Deposition). CVD methods include epitaxial growth, HCVD, PECVD and so on. PVD includes sputtering method and vacuum evaporation method. Generally speaking, PVD has a low temperature, so there is no toxic gas problem. The temperature of CVD is high, and it needs to be above 1000 oC to dissociate gas and produce chemical action. The adhesion of PVD deposition on the surface of materials is worse than that of chemical vapor deposition. PVD is suitable for photoelectric industry, while metal conductive films are mostly deposited by PVD in semiconductor technology, and other insulating films are mostly deposited by CVD technology with strict requirements. The hard film coated by PVD has the characteristics of high strength and corrosion resistance.
(2) Vacuum evaporation deposition is a common film-forming method, which uses resistance heating, induction heating or electron beam heating to evaporate and deposit raw materials on the substrate. The average free path length of evaporated raw material molecules (or atoms) is less than 10 -4 Pa, reaching tens of meters, so it can directly reach the substrate without colliding with other molecules in vacuum. The raw material molecules reaching the substrate have no energy of surface movement and immediately condense on the surface of the substrate. Therefore, when a thin film is deposited on the stepped surface by vacuum evaporation, the surface coverage (coverage) is usually not ideal. However, if Crambo can be evacuated to ultra-high vacuum (
(3) Sputtering deposition The so-called sputtering is a technology that uses high-speed particles (such as argon ions) to hit a solid surface and knock out atoms on the solid surface, and uses this phenomenon to form a thin film, that is, ions in the plasma accelerate to hit the raw material target, and the hit target atoms are deposited on the opposite substrate surface to form a thin film. Compared with vacuum evaporation method, sputtering method has the following characteristics: the step part has good coverage, and a large area of uniform film can be formed. The formed film can obtain a film with the same composition as the composite target, an insulating film and a film with high melting point material, and the formed film has good adhesion with the underlying material. Therefore, both the electrode and the aluminum alloy (Al-Si, Al-Si-Cu) used for wiring are formed by sputtering. The most commonly used sputtering method is to indirectly apply a high-frequency (13.56MHz) power supply to the parallel plate electrode to ionize argon (the pressure is 1Pa), and the atoms sputtered from the target are deposited on the substrate placed on another electrode. In order to improve the film forming speed, magnetic field is usually used to increase the ion density. This device is called magnetron sputtering instrument, which releases inert argon by high voltage, then attracts positively charged ions by accelerating the cathode electric field, hits the target at the cathode, and then deposits the object to be plated on the substrate. Generally, adding magnetic field to increase the free path of electrons can increase the dissociation rate of gas. If the target is a metal, a DC electric field can be used. If it is nonmetal, positive ions can't continue to attract positive ions due to the accumulation of positive charges on the surface of the target, so the problem can be solved by changing to radio frequency electric field (because the oscillation frequency of the field changes too fast, positive ions can't keep up with the change, and the cathode effect appears when the radio frequency is in place). There is a well-known "Moore's Law" in the computer field, which is a manuscript used by Gordon Moore, one of the founders of Intel Corporation, to summarize the growth law of memory chips in 1965 (it is said that he was preparing a speech at that time).
Moore's law is usually quoted by those who are well informed as: "The number of transistors per square inch of silicon wafer doubles every 65438+February." The following are the pictures quoted by Moore in the newspaper of 1965:
The number 1965 quoted by Moore in the newspaper.
The figure shows that the transistor density doubles every 12 months, however, this aspect is not fully discussed in Moore's short paper. Moore's original intention of publishing that paper was to discuss how to reasonably reduce the bulk size of transistors and the manufacturing cost of integrated circuits. More importantly, he knows that this reduction in size will bring great significance: future integrated circuits will be cheaper and have more functions, and more transistors can be integrated, thus making electronic products cheaper and more popular, which will eventually have a great impact on human life and work.
Moore's Law mentions that reducing cost is one of the biggest attractions of integrated circuits, and with the development of technology, the higher the integration, the more obvious the advantage of low cost. For a simple circuit, the cost of each element is inversely proportional to the number of transistors contained in the circuit. But at the same time, with the improvement of integration, the complexity of the circuit will increase, and the manufacturing cost will also increase. Of course, it should be noted that Moore's original work is only four pages, but now the article is much longer. This is because the name "Moore's Law" is not very strict, because it is actually not a scientific or natural law, but at most a law describing the unique development law of exponential growth brought about by the continuous progress of semiconductor production technology.
So what does Moore mean by "complexity of minimum component cost"? What is the relationship between manufacturing defects, manufacturing costs and integration? Let's rewrite the well-known "transistor multiplication law" according to the author's intention: in an integrated circuit chip, the number of transistors involved in minimizing the manufacturing cost of each transistor after conversion will double every year.
After such rewriting, Moore's law may be closer to Mr. Moore's original intention. However, it is still difficult to accurately express the interactive relationship between the cost reduction of each component and the manufacturing cost of integrated circuits caused by the increase of integration. So let's explain it in detail below, so that everyone can understand the essence of Moore's Law more thoroughly. Most readers already know that each chip is cut from a silicon wafer, so we will discuss it from the production process of the chip. The picture below shows a silicon chip with an integrated chip. (The silicon wafer on the right is the silicon wafer used in the 0. 13 micron process P4. )
By using chemical and circuit lithography techniques, transistors are etched onto silicon wafers. Once the etching is completed, individual chips are cut off from the wafer piece by piece.
In the schematic diagram of the silicon wafer, the place marked with yellow dots indicates that there are some defects in this place, or the transistors etched into the silicon wafer have no effect. All this is caused by the limitation of manufacturing process, and any chip with the above problems will be scrapped because it can't work properly. In the above picture, 16 transistors are etched on a silicon wafer, but four of them are defective, so we have to scrap four of the 16 chips (that is, 1/4 of this silicon wafer). If this silicon wafer represents all the silicon wafers produced in our production process, it means that our rejection rate is 1/4, which will lead to an increase in manufacturing costs.
There are two ways to reduce the rejection rate of transistors and improve the current 75% yield rate without substantial improvement of the current manufacturing process. One is to improve our production process, optimize the processing technology and reduce the wafer defect density on each silicon wafer. But before discussing how to reduce the density of bad spots, I think we should spend some time to let you know two basic production parameters of semiconductors-silicon wafer size and etching size.
When a semiconductor manufacturer builds a new chip production plant, you will usually see that it uses these two numbers in the use of related materials: silicon chip size and feature size. Silicon wafer size is the diameter value of silicon wafer used in semiconductor production. Generally speaking, the size of silicon wafers produced by a specific set of silicon wafer production equipment is fixed, because the cost of transforming the original equipment to produce new size silicon wafers is quite amazing, and these costs can almost build a new production factory. Therefore, the wafer size cannot be arbitrarily increased.
You may imagine that the larger the silicon wafer size, the better, so that each wafer can produce more chips. However, there is a characteristic of silicon wafer, which limits the manufacturer to increase the size of silicon wafer at will, that is, the farther away from the wafer center, the more likely it is to have bad spots in the wafer production process. Therefore, from the center of the silicon wafer to the outside, the number of defective points is on the rise. Semiconductor manufacturers always try to control the number of bad spots on the largest wafer. For example, the wafer size used in the manufacture of 8086 CPU was originally 50mm, and now Intel has started to use the 300mm silicon wafer factory to produce a new generation of processors.
As for the etching size, it is the smallest size that the manufacturing equipment can etch on the silicon wafer. So when you hear that P4 adopts the process of 0. 13 micron, it means that the smallest transistor size of Pentium 4 can be as large as 0. 13 micron, which means that the smallest transistor size that this factory can etch on the wafer is 0. 13 micron. You will usually see that the terms "etch size" and "transistor size" can be used interchangeably, because the most important feature on an integrated circuit is the transistor.
The etching size of 8086 is 3u, that of Pentium is 0.8u, and that of Pentium 4 is 0. 13u at present. However, the silicon wafer factory under construction by Intel can etch 0.09u, which is the same as that of silicon wafers. The etching size is fixed, and all silicon wafer manufacturers produce chips according to certain specific etching sizes. Although we will talk more about etching size in this article, we should point out that it is a fixed parameter and will not change frequently. Next, we will explain the silicon wafer size and etching size in more detail through a simple example.