This paper was published in the journal Electronic Measurement Technology 20 15. This paper mainly introduces the design of gigabit Ethernet data transmission system using VC707 development board, which realizes UDP and IP protocols and can use DDR3 for data cache.

The advantages of Ethernet transmission are written. Compared with serial port, the transmission speed is slow, so it can't be transmitted over a long distance. PCIE can't transmit over a long distance, so Ethernet is chosen considering the characteristics of transmission rate and flexible system use.

Advantages of choosing the FPGA development board VC707 from Xilinx company xc7vx485T.

1 integrates MAC hard core and SGMII interface, which can realize MAC layer function and PHY layer interface.

2. The integrated chip of PHY layer can complete the functions of PHY layer.

3. It integrates 1gb DDR3 resources and can cache data.

The overall design scheme is shown in the figure, in which the SGMII interface between MAC layer and PHY layer can be realized by directly calling IP.

Receiving module

Accept the ARP request of the host, extract the MAC address and IP address of the host, receive the UDP packet of the host, and extract the message.

Sending module

Send ARP reply to the upper computer, package the data to be sent, add UDP header, ip header and Ethernet frame header, and send it to the IP core of MAC layer.

DDR3 control module

The data in the receive FIFO is stored in DDR3, and is read out from DDR3 to the transmit FIFO at the time of transmission.

Transmit/receive FIFO

The working clock of Ethernet is 125 MHZ, and that of DDR3 is 200MHZ. These two FIFO are used to solve the problem of cross-clock domain.

MAC layer IP core

Complete the encapsulation and decapsulation of Ethernet frame preamble and frame start delimiter.

Specific workflow: when sending data, the system encapsulates the data in DDR3 through sending logic and ip core of MAC layer, then sends the output data to PHY chip through IP core of SGMII interface, and sends the data to the upper computer through RJ45 interface after the data is encoded in PHY layer; Receiving data by the system is the reverse process of sending data. The data sent by the host computer reaches the PHY chip through RJ45 interface, and is received and output through SGMII interface after being decoded at PHY layer.

The IP core and receiving logic module sent to the MAC layer complete data extraction or instruction execution, and the data is stored in DDR3.

ARP protocol is introduced later, not to mention IP protocol and UDP protocol.

ARP is to get the destination MAC address, so that IP and UDP can be sent to the destination correctly.

This module is mainly used to distinguish whether the received module is ARP or UDP.

There are three main points in identifying ARP:

1. Determine whether the destination MAC address is FF-FF-FF-FF-FF-FF.

2. Determine whether the frame type is 0X0806.

3. Judge whether the operation code is 1.

If yes, generate ARP_request signal, extract the MAC address and IP address of the upper computer, and output it to the ARP processing module.

When judging whether it is UDP:

Is the protocol field of 1.IP datagram header 0x 1 1?

2. Is the destination IP address of the IP packet the same as the local address?

3. Is the destination port number of 3.udp header the same as the local port number?

If the judgment is passed, UDP data is stored in the receiving FIFO, and the length of the recorded data is frame_cnt.

There are two kinds of data to send, namely ARP reply and data read from DDR encapsulated into UDP MAC frame data.

The state machine is shown in the figure.

1. When the ARP processing module outputs ARP_reply, it enters the ARP reply frame state, and after the reply is completed, it enters the idle state. At this time, the ARP processing module needs to provide the MAC address and IP address of the upper computer in the reply state.

2. When the state machine detects DDR_RD_CPL signal, that is, DDR3 has data stored in the transmit FIFO, it starts to add MAC header, IP header and udp header, and finally reads the data in the FIFO, and the state machine enters an idle state.

Finally, there are some calculations. Because the destination, source MAC, ip and port number have all changed, it is necessary to recalculate the IP checksum, UDP checksum and statistical data length, and package the results into data packets.

Finally, the new harvest is that in full-duplex mode, the data length of Ethernet frame can't exceed 1500 bytes, minus 20 bytes of IP header and 8 bytes of udp header, then the udp data length should be less than 1472 bytes.