First of all, the first point: FPGA price division. Just follow altera's advice.

Devices of EP2C cyclone2. 35 represents the number of lookup tables contained therein, which is equivalent to the number of 350x4k gates. There are still two parameters you haven't seen. 1. packaging, 2. Equipment speed. Discuss separately.

Packaging is a specific constraint of pins. Such as 240, 256, 424, 676 and the corresponding pin package forms. Such as FBGA and so on. The specific writing is as follows. Xx240 represents a 240-pin FPGA in a package.

The second is the speed level. Altera's speed level can be between 6 and 8. 8 is the slowest. 6 stands for fastest. The speed level directly affects the highest clock frequency that your design can run. (This is just an external cause. In fact, your design style affects the clock frequency more.

The rest. According to different series of FPGA. The corresponding power consumption is different from the internal dedicated structure. It will also lead to different prices.

According to this train of thought. The standard of price division is:

1, the higher the number of equivalent gates. The higher the price.

2. The more 2.IO ports there are. The higher the price.

3. The faster the speed. The higher the price.

4. The price with special devices is higher than that without special devices (DSP or CPU).

5. Low power consumption is higher than the price of high power consumption.

Hehe, the door you see is 15W. 200 yuan. I don't know what model. But if it is cyclone2, I think it is a little expensive.

Then the second question: the estimation of FPGA.

According to your example: 10 decimal counter. You may need two look-up tables and four D triggers.

According to the number of lookup tables x4+the number of D flip-flops x2, it is estimated to be a circuit with about 16 gates.

By the way, the estimation of FPGA. The prediction of FPGA is divided into the following points:

1, logical resource estimation. When you finish writing the code. Look at the comprehensive report after synthesis. The use of internal resources of FPGA will be very accurate.

2.IO port estimation: The estimation of IO port is to calculate whether the fixed IO port in the bank is enough. There is the concept of BANK in FPGA. When different VCC are connected, there are fixed VCC and GND on this shore. For example: TTL. Then all pins on the corresponding bank output TTL levels. For example, you need to calculate how many pins there are in CMOS. So there are several banks. How many pins are there in TTL and LVDS, etc. How many banks do you need to occupy? Finally, see if it is not enough. . If it is not enough, it needs to be replaced.

3. Power estimation: Power estimation is actually a complicated part in FPGA. Fortunately, all major companies have introduced the estimate excle table. With instructions for use. I won't go into details here.

4. After work. You also need to know the cycle of goods adjustment (this is mainly for agents. If the cycle of goods adjustment is long, you can change it. But this thing is like a computer. Different agents. The price is also different. In case you choose an FPGA that is not very mainstream, and then you have a zero emergency purchase. So ... . .

Finally, I wish you an early academic success.

-I found it for you.

I have seen a teacher's own development board, which is either very complicated or has many pins. I don't know if you are an undergraduate. Bi can use FPGA chip or directly use development board, as long as you have your program.