SPI: high-speed synchronous serial port

SPI: high-speed synchronous serial port. This is a standard four-wire synchronous bidirectional serial bus.

SPI is the abbreviation of English serial peripheral interface, which is the serial peripheral interface as its name implies. It was first defined by Motorola on its MC68HCXX series processors. SPI interface is mainly used for EEPROM, FLASH, real-time clock, AD converter, and between digital signal processor and digital signal decoder. SPI, a high-speed, full-duplex and synchronous communication bus, only occupies four wires on the pins of the chip, which saves the pins of the chip and space, and provides convenience for the layout of PCB. It is precisely because of this simple and easy-to-use feature that more and more chips integrate this communication protocol, such as AT9 1RM9200.

SPI bus system is a synchronous serial peripheral interface, which enables MCU to communicate with various peripherals in serial mode to exchange information. The periphery is equipped with FLASHRAM, network controller, LCD display driver, A/D converter and single chip microcomputer. SPI bus system can directly interface with various standard peripherals produced by various manufacturers. Generally, the interface uses four lines: serial clock line (SCLK), master input/slave output data line MISO, master output/slave input data line MOSI and low-level slave selection line SS (some SPI interface chips have interrupt signal line INT, and some SPI interface chips have no master output/slave input data line MOSI).

The communication principle of SPI is very simple. It works in master-slave mode. This mode usually has a master device and one or more slave devices, and at least four wires are required. In fact, three lines can be used (unidirectional transmission, that is, half-duplex mode). It is also applicable to all SPI-based devices. They are SDI (data input), SDO (data output), SCLK (clock) and CS (chip selection).

(1) MoSi–SPI bus master output/slave input.

(2) MISO–SPI bus master input/slave output.

(3) SCLK clock signal generated by the master device.

(4) CS–The enabling signal of the slave device is controlled by the master device.

In which CS is used to control whether to select a chip, that is, the operation of the chip is effective only when the chip selection signal is a pre-specified enable signal (high potential or low potential). This makes it possible to connect multiple SPI devices on the same bus.

Next, we will be responsible for three communication lines. Complete communication through data exchange. The first thing to know here is that SPI is a serial communication protocol, which means that data is transmitted bit by bit. This is why the SCLK clock line exists. SCK provides clock pulse, and SDI and SDO complete data transmission based on this pulse. Data is output through SDO line, which changes at the rising or falling edge of the clock and is read at the subsequent falling or rising edge. To complete a bit of data transmission, the same principle is used for input. In this way, the clock signal changes at least 8 times (once on the upper edge and once on the lower edge) to complete the transmission of 8-bit data.