MMU is the abbreviation of memory management unit, and its Chinese name is memory management unit. MMU is the computer hardware responsible for the memory access request of the processor (CPU), and its functions include the conversion from virtual address to physical address (virtual memory management), memory protection, cache control and so on.
MMU is a hardware component closely related to software, and it is also one of the largest components running linux and other operating system kernel mechanisms that rely on MMU memory management unit. If the processor does not have MMU, the memory address signal generated by the internal execution unit of CPU will be directly sent to the chip pin through the address bus and received by the memory chip, that is, the physical address (PA for short). English physical stands for physical contact, so PA is a signal on the bus that is physically connected to the memory chip.
If MMU exists and is enabled, the address signal generated by the CPU execution unit will be intercepted by MMU before being sent to the memory chip. This address signal is called virtual address (VA for short), and MMU will be responsible for translating VA into another address and then sending it to the address pin of the memory chip, that is, VA is mapped to PA.
2.PowerPC E500 MMU
Powerpc (performance optimization with enhanced RISC–performance computing, sometimes abbreviated as PPC) is a CPU with reduced instruction set (RISC) architecture, and its basic design is derived from IBM's Power (performance optimization with enhanced RISC).
PowerPC chip is widely used in network communication applications, industrial control applications, home digitalization, network storage, military industry, power system control and other fields because of its excellent performance, high integration and advanced technology.
PowerPC E500 is a 32-bit microprocessor core of Freescale based on Power architecture. There are three versions of E500 series kernel, namely E500v 1 and E500mc of E500v2. The 64-bit version of E500mc evolved into E5500 core, which was launched at 20 10.
PowerPC E500 core (hereinafter referred to as "E500") adopts two-level memory management unit (MMU) architecture. L 1-MMU and L2-MMU are two hardware units in this structure. E500 uses L 1-MMU and L2-MMU, and some auxiliary registers and instructions to realize the conversion of virtual and real addresses. The core of E500v 1 is to convert 32-bit effective address into 32-bit physical address (using 4 1 temporary virtual address); The core of E500v2 is to convert a 32-bit effective address into a 36-bit physical address.
L 1-MMU features:
1. Two fully associative TLB arrays with four entries (one for instruction access and one for data access) support nine (E500v 1) or1(E500V2) page sizes, namely I-L 1VSP and D.
2. Two 64-entry, 4-way group associative TLB arrays (one for instruction access and one for data access) only support 4kb pages, namely I-L 1TLB4K and D-L 1TLB4K.
3.L 1 MMU access and L 1 cache access (address translation /L 1 cache) can be completely pipelined, so that each clock can complete loading/storage once.
4. The instruction access and data access of L1TLB lookup are parallel.
5. All L 1 TLB entries are appropriate subsets of TLB entries located in L2 MMU.
6. Automatically perform invalidation operations to keep the consistency of L2 TLB.
L2-MMU features:
1. 16 entries, fully associated unified L2 TLB array (for instruction and data access) TLB 1 supports 9 (E500v 1) or1(E500V2) page sizes, that is, TLB/.
2.256 The associated unified L2 TLB array (TLB0) of entry 2-way (E500v 1) or entry 4-way (E500v2) set of 5 12 only supports 4kb pages, that is, TLB0 for page mapping.
3. Support for Miss TLB is an exception.
4.TLB 1 and TLB0 are managed by tlbRe, tlbwe, tlbsx, tlbivax and mtspr instructions.
5. The execution of TLB 1 and TLB0 generated by the current kernel tlbivax instruction is invalid. Support other cores to execute TLB 1 and TLB0 invalid operations caused by tlbivax instructions.
6. The IPROT bit implemented in TLB1prevents invalidation, thus protecting the key entry (specified by setting the IPROT bit) from invalidation.
2. 1 effective to real address conversion process
The conversion process from effective address to real address is as follows:
Because the minimum page size of E500 is 4K bytes, the low 12 bits are usually used as indexes within 4K pages, and no conversion is needed. First, check whether L 1 MMU (instruction or data) hits the address translation. If not, the translation request will be forwarded to L2 MMU (instruction and data) for processing.
See the table below for the page sizes supported by E500v 1 kernel and E500v2 kernel. Compared with E500v 1 kernel, E500v2 kernel supports 1 GB and 4gb page sizes.
2.2 MMU input fields
In TLB, data is stored in rows, and one row is called an entry. An entry contains several bits. The following is a description of the bit meaning of the MMU entry:
V: used to indicate whether the current entry is valid. 0 means invalid, 1 means valid. After the system is reset, the V bit of all entries is set to 0.
TS: It's the same as the address space above. 0 means address space 0, 1 means address space 1.
Tid [0: 7]: PID in the address space above. When TID is 0, the comparison of PID is ignored. In Linux, all zeros.
EPN [0: 19]: Virtual page frame number. The effective number of pages is different according to the page size.
RPN [0: 19]: physical page frame number.
Size [0: 3]: indicates the page size of the current entry.
Permi[0:5]: used to describe the access control bits of the current entry. They are ur, SR, UW, SW, UX, SX. Represents read/write/execute permissions in user mode and kernel mode respectively.
Wimge [0: 4]: w indicates whether the current entry is written directly or back. Indicates whether the current entry ignores caching. M indicates that access to this data area requires storage consistency processing. G represents the operation protection of the corresponding storage area. E indicates whether the current entry is small or large.
X0, X 1: Describe some additional properties.
U [0: 3]: Custom purpose.
IPROT: when IPROT is 1, it means that the current entry is protected. You cannot use the tlbivax instruction to invalidate an entry. Cleared by tlbwe instruction only. In E500, only TLB 1 supports this bit, and in TLB0, this bit is always 0.
The instructions, registers and exceptions related to TLB are shown in the following table:
2.3 MMU related registers
Pid0-2 register: used to store the Pid of the current process. This register is valid only for bits 54-63.
MMUCSR0 register: used to invalidate all entries of TLB0 and TLB 1. The L2TLB0_FI bit of this register invalidates all entries; TLB0; The L2TLB 1_FI bit invalidates all entries of TLB 1.
MMUCFG register: used to store the current MMU configuration information, including the number and size of PID registers, the number of TLB, etc.
TLB0CFG and TLB 1CFG registers: used to describe the configuration information of TLB0 and TLB 1, including the number of entries, page table size and other information.
MAS auxiliary registers (mas0–mas4, mas6–mas7, without MAS5) are mainly used to maintain TLB entries in MMU.
MAS0 register: which entry determines which TLB to write. The TLBSEL field is used to select the TLB to be operated, with 0 indicating TLB0 and 1 indicating TLB 1. The ESEL field is used to select TLB entries. When TLB 1 is used, the lower 4 bits of the ESEL field are valid for selecting the entry in TLB 1. When using TLB0, only the lowest bit of ESEL is valid, because TLB0 is connected by two groups. The NV bit is used to determine how to replace the entry in TLB0.
The fields stored in MAS 1-3 correspond to the fields in TLB entries.
MAS4 register
This register is mainly used to store the default value used to automatically load the MAS 0-3 register when a TLB miss exception occurs, that is, the contents of the MAS4 register are written by hardware. In order to improve the efficiency of TLB miss exception, E500 will automatically fill some contents of MAS0-2 register with the value in MAS4 register when the exception occurs:
MAS 0[TLBSEL]& lt； - MAS4[TLBSELD]
MAS 1[TID]& lt； - MAS4[TIDSELD]
MAS 1[TSIZE]& lt； - MAS4[TSIZED]
MAS2[X0，x 1]& lt； - MAS4[X0D，X 1D]
MAS 2[WIMGE]& lt； - MAS4[WD，ID，MD，GD，ED]
MAS6 register: used to retrieve TLB. MAS6 register provides SPID0 and SAS, namely PID and AS domains.
MAS7 register (only supported by E500v2): The high-order address bits containing the implemented RPN support physical addresses exceeding 32 bits.
2.4 TLB related instructions and their execution
SkyEye, the full name of the Chinese digital real-time simulation software, is a hardware behavior level simulation platform based on visual modeling, which supports users to simulate and model the hardware behavior level by dragging and dropping. SkyEye supports instruction set simulation of E500 processor based on PowerPC architecture. In order to support the operation of operating systems (such as VxWorks, Linux, etc.). ) contains MMU unit, which needs to realize the simulation function of MMU, including instruction realization related to TLB(Translation Lookaside Buffer) and MMU virtual-real translation process.
The explanation related to TLB is as follows:
Tlbre instruction: The tlbre instruction reads the contents of each field of a single TLB entry from L2 MMU and writes it into the corresponding field of MMU auxiliary (MAS) register. The read entry is specified by TLBSEL, ESEL and EPN fields of MAS2 register of MAS0. When reading TLB 1, ESEL is valid and EPN is invalid; When reading TLB0, ESEL upper 2 bits are valid and EPN is valid. Note that for E500v2, if HID0 [en _ MAS7 _ UPDATE] = 1, MAS7 is also updated as the physical address of the TLB entry.
Tlbwe instruction: This instruction extracts the contents of each field from MMU auxiliary register (MAS) and writes it into a single TLB entry in L2 MMU. The written entry is specified by TLBSEL, ESEL and EPN fields of MAS2 register of MAS0. When writing TLB 1, ESEL is valid and EPN is invalid; When writing TLB0, ESEL upper 2 bits are valid and EPN is valid. Note that for E500v2, the RPN field in MAS7 is also written into the selected TLB entry.
Tlbsx instruction: the instruction format is tlbsx RA, RB. The function of this instruction is to use the address of ra+Rb to find TLB through MAS6 register, and if it hits, put the result into MAS 0-3 register.
Instruction realization:
Tlbivax instruction: TLB invalid operation. This instruction will invalidate all TLB entries corresponding to the calculated virtual address, and also invalidate TBL entries contained in TLB on other processors.
According to the Bit6 1 of the effective address EA, it is judged whether all the entries are invalid, if not, the corresponding entries are calculated, and then entry->; V = 0 is used to invalidate the entry.
Tlbsync instruction: This instruction is used to synchronize the reading and writing of TLB entries. The main purpose is to broadcast the updated entries of tlbivax instruction to the system bus to synchronize other processors. This instruction is only valid in SMP systems.
2.5 TLB initial state after system reset
After reset, all TLB entries in L 1 and L2 MMU are invalid, and the first entry of TLB 1 needs to be initialized and assigned, as shown in the following figure:
References:
[ 1] PowerPC？ E500 core series refers to Manual.pdf.