1, design tasks and requirements:
Design task: design a digital clock that can display hours, minutes and seconds. The specific requirements are as follows:
The second pulse is generated by frequency division of the clock signal on the experimental box;
24-ary timing circuit of timing counter;
Time can be corrected manually, and time and minutes can be corrected separately;
Tell the time;
2 program code and corresponding waveform
Seconds 1 (seconds in hexadecimal and 10)
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity seconds 1 Yes
Port( clks，clr:in STD _ logic；
Secs，Secg:out STD _ logic _ vector(3 down to 0)；
cout 1:out STD _ logic)；
end second 1；
The architecture a of second 1 is
begin
Process (clock, clock)
The variable ss, SG: STD _ logic _ vector (3downto0);
The variable co:STD _ logic；;
begin
If clr=' 1', then ss:= "0000 "；; SG:= " 0000 "；
Elsif clks event and clks=' 1' and then
If ss="0 10 1 "and sg=" 100 1", then ss:= "0000 "；; SG:= " 0000 "； co:= ' 1 '；
Elsif SG< "1001"Then SG: = SG+1; co:= ' 0 '；
Elsif sg=" 100 1 "Then SG:=" 0000 "；; ss:= ss+ 1； co:= ' 0 '；
End if;
End if;
cout 1 & lt； = co
Secs & lt= ss
Secg & lt= sg
End the process;
End a;
Min 1 (hexadecimal sub-counter and decimal ALM 10 can tell hours)
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity min 1 Yes
Port(clkm，clr:in STD _ logic；
mins，Ming:buffer STD _ logic _ vector(3 down to 0)；
enmin，alarm:out STD _ logic)；
End;
The architecture a of min 1 is
begin
Process (clkm, clr)
The variable ms, mg: STD _ logic _ vector (3downto0);
Variables so, ALM:STD _ logic；;
begin
If clr=' 1', then ms:= "0000 "；; mg:= " 0000 "；
Elsif clkm' event and clkm=' 1' then
If ms="0 10 1 "and mg=" 100 1", then ms:= "0000 "；; mg:= " 0000 "； So: ='1'; ALM:= ' 1 '；
Elsif mg< "1001"Then mg: = mg+1; So: =' 0'; ALM:= ' 0 '；
Elsif mg=" 100 1 "Then mg:=" 0000 "；; ms:= ms+ 1； So: =' 0'; ALM:= ' 0 '；
End if;
End if;
Alarm & lt= alm
Enmin < = so;
Minute & lt= ms
Ming & lt= mg
End the process;
End a;
Hour 1 (quaternary and binary hour counters)
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity hours 1 Yes
Port(clkh，clr:in STD _ logic；
Hours, hourg:out std_logic_vector(3 down to 0));
End;
The architecture a of hour 1 is
begin
Process (clkh, clr)
The variable hs, Hg: STD _ logic _ vector (3downto0);
begin
If clr=' 1', then hs:= "0000 "；; Hg:= " 0000 "；
elsif clkh ' event and clkh = ' 1 ' then
If hs="00 10 "and hg="00 1 1", then hs:= "0000 "；; Hg:= " 0000 "；
Elsif Hg< "1001"Then Hg: = Hg+1;
Elsif hg=" 100 1 "Then Hg:=" 0000 "；; hs:= hs+ 1； End if;
End if;
Hours & lt= hs
hourg & lt= hg
End the process;
End;
proofread
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
The entity madapt is
Port(en，clk，secin，m 1:in STD _ logic；
minset:out STD _ logic)；
End;
Madapu's building a is
begin
Process (en, m 1)
begin
If en=' 1', then
If m 1=' 1', then min set < = clk.
Elseminset < = secin ends if;
else minset & lt= secin
End if;
End the process;
End;
School time
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity hadapt is
Port(en，clk，minin，h 1:in STD _ logic；
hourset:out STD _ logic)；
End;
Hadap's building a is
begin
Process (en, h 1)
begin
If en=' 1', then
If h 1=' 1', then hour < = clk.
Elsehour & lt = minin ends if;
else hourset & lt= minin
End if;
End the process;
End;
Topclock (component instantiation top-level file)
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Entity topclock is
Port(clk，clr，en，m 1，h 1:in STD _ logic；
alarm:out STD _ logic；
secs，secg，mins，ming，hours，hourg:buffer STD _ logic _ vector(3 down to 0))；
End;
One of the architectures of topclock is
Component sec 1
Port( clks，clr:in STD _ logic；
secs，secg:buffer STD _ logic _ vector(3 down to 0)；
cout 1:out STD _ logic)；
End assembly;
Component min 1
Port(clkm，clr:in STD _ logic；
mins，Ming:buffer STD _ logic _ vector(3 down to 0)；
enmin，alarm:out STD _ logic)；
End assembly;
Component hours 1
Port(clkh，clr:in STD _ logic；
Hours, hourg:buffer std_logic_vector(3 down to 0));
End assembly;
Component madapt
Port(en，m 1，clk，secin:in STD _ logic；
minset:out STD _ logic)；
End assembly;
Component hadapt
Port(en，h 1，clk，Minin:in STD _ logic；
hourset:out STD _ logic)；
End assembly;
Signals a, b, c and d: STD _ logic;
begin
U 1:second 1 port mapping (clr = & gtclr,
secs = & gtsecs，secg = & gtsecg，clks = & gtclk，cout 1= >a)；
U2:min 1 port mapping (clr = & gtclr, alarm => alarm,
Minute = & gtmins, ming => Ming, clkm =>b, enmin =>C);
U3:hour 1 port mapping (clr = > clr,
hours = & gthours，hourg = & gthourg，clkh = & gtd)；
U4: map of MAdapt port (en = & gten, m 1= >m 1, clk = & gtclk, secin =>a, min set =>B);
U5:hadapt port mapping (en = & gten, h 1= >h 1, clk = & gtclk, minin =>c, hourset =>D);
End;
3 circuit diagram
4 experimental experience
All the programs are written for you. You just need to simulate it yourself, download it into the experimental box, and it's OK.