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Connect. Because the storage form chosen by NOR Flash is 5 12K× 16Bit, which is the minimum value of NOR Flash.
The storage unit is 2 bytes, and the minimum addressing unit of S3C2440 is 1 byte, so it is necessary to change the address line.
The second ADDR 1 is connected to A0, and ADDR0 is not connected to NOR Flash chip.
(2) 16 bit data lines are connected in turn. The port DQ 15/A- 1 has two purposes. If NOR flicker
Chip chooses 1024K×8Bit storage mode, and this port will be the lowest address line, which is selected in this paper.
The storage mode of 5 12K× 16Bit is selected, so this port is the highest bit DQ 15 of the data line.
(3)CE is the chip selection signal. Since NOR Flash is connected to BANK0, BANK0 is required.
Chip select signal nGCS0. Read enable OE and write enable WE are connected to the corresponding pins of S3C2440.
(4)RY/BY indicates whether NOR Flash is ready or busy, which is not used here.
So I hung up. The reset is active at low level and connected to the reset module of the circuit.
(5)BYTE is the choice of reading and writing mode of NOR Flash chip, with high level corresponding to 16bit mode and low level corresponding.
This level corresponds to the 8-bit mode. In this paper, 16 bit mode is adopted, which is directly connected to VDD.
(6)OM0, OM 1 is the choice of S3C2440 startup mode. When OM0= 1, OM 1=0 chipset.
It is 16 bit, and the NOR Flash chip is mapped to address 0x0 of BANK0. S3C2440
There are two ways to start NOR Flash: 16bit and 32bir, so only Am29LV800D is introduced.
You can use 16bit read-write mode, but you can't use 8bit mode.
NOR Flash reads and writes in the same way as memory, and can read and write directly within its address range.
So copy the startup program into NOR Flash, and it can be run directly after power-on. But there was no flash.
The price is expensive, and the capacity of 1M is not enough, so this system also adds a NAND Flash chip.
As a supplement.
2.4.2 NAND flash memory circuit design
Compared with NOR flash memory, NAND flash memory is much cheaper, so it is more suitable for comparison.
The use of mass storage media. 1989, Toshiba released NAND Flash technology (later
Technology is transferred to South Korea's Samsung Company for free), and NAND Flash technology emphasizes reducing the cost per bit, which is higher.
Performance, and like a disk can be easily upgraded through the interface. NAND flash memory structure can provide extremely high
The cell density can reach a high storage density, and the speed of writing and erasing is also very fast. Its disadvantage is that
Yu needs a special system interface, and CPU needs a driver to read data from NAND Flash.
According to reports, in use, data is generally copied from NAND Flash to SDRAM, and then CPU sequence.
Execution, which is why most embedded systems can't start from NAND Flash.
S3C2440 not only supports booting from NOR Flash, but also supports booting from NAND Flash. This is the master's degree thesis of Wuhan University of Technology.
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Because when NAND Flash is started, 4k data in Flash will be automatically recovered by S3C2440.
Make a RAM called "Steppingstone" inside the chip, and set 0x0 as the internal RAM.
The starting address of, and then the CPU starts execution from 0x0 position of internal RAM. This process does not need a process.
Order interference. And the program can use this 4k code to copy more data from NAND Flash to.
SDRAM to start with NAND Flash.
To choose whether to boot from NOR flash or NAND flash, OM0 and OM 1 are required.
The pin settings are different. If it is often necessary to switch the startup mode, you can connect these two pins to the jumper.
On the post, fix it with jumper clips.
In this paper, the K9F 1208U0B NAND Flash chip produced by Samsung is selected. Chip capacity
It's 64M×8bit. Because S3C2440 has built-in NAND Flash controller, the circuit design is X.
The division is simple and no additional control chip is needed. The circuit diagram is shown in Figure 2-4.
Figure 2-4 Circuit diagram of NAND flash memory
Description of circuit diagram:
(1) Because NAND flash memory chips are stored in bytes, the data line I/O0-7.
The data line DATA0-7 directly connected to S3C2440 does not need to be shifted by one bit like NOR Flash.
Line connection. I/O0-7 is a port for address, command and data multiplexing.
(2)ALE data latch allow, CLE command latch allow, CE chip select, WE write enable, RE.
The read enable is connected with the pins ALE, CLE, nFCE, nFWE,
NFRE is connected.
(3)WP write protection, which is not used here, is directly connected to high level to make it invalid. VCC and power supply
Connect, VSS ground. Master's degree thesis of Wuhan University of Technology
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(4) When OM0 and OM 1 are grounded to 0, S3C2440 will start from NAND Flash.
The internal RAM“stepping stone "will be mapped to 0x0 position, replacing the original NOR in this position.
Flash. The first 4K data in NAND flash memory will be automatically copied to Stepping Stone when it is powered on.
So as to start with NAND flash memory.
(5)NCON, GPG 15 are grounded; GPG 13 and 14 are connected to the power supply. These four pins are used for NAND.
Flash settings. The above settings indicate that the Flash used is ordinary NAND Flash, and the size of a page is.
5 12, it takes four weeks to complete the address transmission and turn it into an address lookup operation (this is because
K9F 1208U0B chip adopts 26-bit addressing mode, and goes through I/O0-I/O7 four times starting from bit 0.
Line transmission), and the data bit width is 8 bits. Different chips have different settings. The above is K9F 1208U0B.
For the setting method of, other chips need to refer to S3C2440 and specific NAND Flash.
Chip data sheet
NAND Flash does not correspond to any memory bank, so it cannot be used for bus operation.
It can't be accessed directly by address like NOR Flash and SDRAM. Yes, NAND flash memory
The operation of memory chip must be completed through the special register of NAND Flash controller.
The writing operation of NAND Flash must be carried out in blocks, and the reading operation can be read in bytes.
For K9F 1208U0B, register the command register (for S3C2440, this register
For NFCMMD, the memory mapping address is 0x4e000004), and the command queue 1 is implemented.
Generally speaking, there are several consecutive commands or a command plus several parameters. Please refer to K9F 1208U0B for specific commands.
Data table of. The address register decomposes the complete NAND flash address into column addresses.
An address with a page address. Column address is a column address, which is used to specify the specific on the page.
One byte. The page address is the page address, which is used to determine which page of the flash memory the read-write operation is on.
Line, because the page address is always aligned with 5 12 bytes, its low 9 bits are always 0.
A0~A7 in the 26-bit address is its column address, and A9~A25 is its page address. When sending
After the command ends (for example, read command 00h or 0 1h), the address will be sent within four cycles. The first cycle is hair.
Delivery address. The next three cycles are used to specify the page address. After sending the address, you can transfer the data.
Registers read and write data to NAND flash memory. The above is just the NAND Flash control of S3C2440.
The general operation flow and specific operation mode of the equipment need to refer to the data manual.
2.4.3 SDRAM memory circuit design
Reading data from Flash is slow, while S3C2440 runs very fast.
The speed of line instructions is much higher than that of reading instructions from Flash. If we only look at the data from Flash, Wuhan University of Technology Master thesis
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Then the system is designed by chip processing, so that even if the computing power of the chip is strong, there are no fingers.
In case of execution, it will have to wait. Therefore, it is necessary to add SDRAM to the system.
Sdram (Synchronous Dynamic Random Access Memory) is synchronous dynamic random.
Access to memory, synchronization refers to the need to synchronize the working clock, internal command transmission and data transmission.
Based on this, dynamic means that the storage array needs to be constantly refreshed to ensure that data is not lost, while random means.
Data is not stored in linear order, but read and written at the specified address.
SDRAM is a dynamic memory, which works synchronously with the system clock. It has the advantages of high data throughput and high speed.
Fast, cheap and so on. The main function of SDRAM in the system is as the running space of program code.
When the system starts, the CPU first reads the startup code from the reset address. After completing the system initialization,
Transfer the program code to SDRAM to run, so as to improve the running speed of the system. At the same time, the system and users
Stack and operation data are also stored in SDRAM.
Due to the structural characteristics of SDRAM, it needs to be refreshed regularly, which requires the hardware circuit to be available.
The function of timing refresh, S3C2440 chip integrates an independent SDRAM control circuit on the chip, which can
It is convenient to connect with SDRAM, and the system runs stably.
The SDRAM chip model used in this design is HY57V56 1620, and its storage capacity is 4Bank×4M.
×l6bit, each library is 8M bytes, and the total size of * * * is 32M. The system consists of two pieces of HY57V56 1620.
A 64MB SDRAM storage system is constructed, which can meet the needs of embedded operating systems and more complex algorithms.
Operational requirements. The circuit diagram is shown in Figure 2-5.
Figure 2-5 SDRAM circuit diagram
Description of circuit diagram:
(1) This system uses two HY57V56 1620 chips to form SDRAM with a capacity of 64M. two
SDRAM is stored in units of 2 bytes, so the minimum storage capacity at a time is 4 bytes. will
The data line DQ0-DQ 15 of the chip is connected with the data line DQ0-DQ 15 of S3C2440.
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The other block is connected with the high bit DATA 16-DATA3 1 of the data line.
(2) The address lines of the two SDRAM chips are in sequence with the address lines ADDR2-ADDR 14 of S3C2440.
Connect. Inside SDRAM is a storage array which is filled with data like a table.
Like the retrieval principle of a table, first specify a row, then specify a column, and then
You can find the required cell accurately, which is the basic principle of memory chip addressing. Just because, for example,
Here, the address is transmitted by dividing the row address and the row address of the memory cell into rows. Therefore,
HY57V56 1620 only needs 13 address lines to address a memory bank (8M size). no
Then according to the normal 8M address space and byte transmission, 24 address lines are needed.
Because this system consists of two 16-bit chips, the minimum storage unit is 4 bytes at a time, that is to say
The addressing interval should be 4(2
2
) bytes. The interval of ADDR0 corresponds to 1 byte, and ADDR 1 is two words.
Segment, ADDR2 is 4 bytes. Therefore, HY57V56 1620 needs to be connected from ADDR2 to get there.
The interval to an address is 4 bytes.
(3)HY57V56 1620 consists of four banks, each of which is 8M(4M× 16bit).
Therefore, addressing is also needed between different banks. Because the size of the bank is 8M=2.
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, because
This pair of memory bank spaces with an interval of 8M requires the use of two address lines starting from ADDR24.
Therefore, BA0 and BA 1 are connected to ADDR24 and ADDR25, respectively.
(4)LDQM and UDQM are data input and output shields, which are controlled by SDRAM controller of S3C2440.
Use, where the chip connecting the lower data line is connected to DQM0, dqm1; And connected to higher-order data.
The chip of this line is connected to DQM2 and DQM3. Please refer to the data sheet of S3C2440 for specific connection methods.
(5) The chip selection signal CS is connected to the chip selection signal nSCS0 of SDRAM, and the two chips have the same correspondence.
Chip selection signal. This is because the two chips are connected at high and low levels in the same place.
Address space.
(6)RAS row address strobe signal, CAS column address strobe signal, WE write enable, and
Connect corresponding control pins nSRAS, nSCAS and nWE of S3C2440. Clock signal
The clock enable signal is connected to SCKE and SCLK respectively.
Before using the program to read and write SDRAM, it is necessary to initialize SDRAM and set some configuration registers.
Settings. Only BANK6 is used here, and BANK7 is not used.
The code for initialization is roughly as follows:
Void memory setting (void)
{
rBWSCON = 0x 22 1 1 1 1 10； Master's degree thesis of Wuhan University of Technology
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rBANKCON0 = 0x700
rbankcon 1 = 0x 700；
rBANKCON2 = 0x700
rBANKCON3 = 0x700
rBANKCON4 = 0x700
rBANKCON5 = 0x700
rbankcon 6 = 0x 18005；
rbankcon 7 = 0x 18005；
rre fresh = 0x8e 07 a 3；
rBANKSIZE = 0xb2
rMRSRB6 = 0x30
rMRSRB7 = 0x30
}
The BWSCON register is mainly used to set the bit width here, where every 4 bits describe a bank.
In this system, two SDRAM with a capacity of 32 MB and a bit width of 16 are used to form the capacity.
It is a memory with 64 MB bytes and a bit width of 32, so it is necessary to set BANK6 to 32 bits. Bank account 0-5
No, just use the default value of 0x700. BANKCON6-7 is used to set SDRAM, which is set to
0x 18005 indicates SDRAM external connection, and the number of column address bits is 9. The refresh register is used to set.
Set the refresh cycle of SDRAM, and refer to HY57V56 1620 data sheet for the value of refresh cycle.
BANKSIZE sets the size of BANK6 and BANK7. Address spaces corresponding to BANK6 and BANK7.
Different from BANK0~5. The address space size of BANK0~5 is fixed, 128M, starting from BANK7.
The starting address is variable, and the system only uses 64M space of BANK6, so it can register.
When bit [2: 0] = 010 (128m/128m) or 00 1(64M/64M), redundant space will be detected.
Non-existent memory will not be used, because both Bootloader and Linux kernel will check the memory.
2.4.4 Circuit design of touch screen
Using touch screen TSP (touch screen panel) for input means touching with fingers or other objects.
Touch the touch screen installed in front of the display, and control the touch position (in the form of coordinates) through the touch screen.
The equipment is detected and sent to the CPU through the interface, so as to determine the corresponding information input. Touch screen through some kind of
The physical mechanism enables users to directly control the display with the touch screen instead of the traditional one.
Based on [14], input information to the computer through mouse and keyboard control.
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Touch screen can be divided into vector pressure sensing type, resistance type, capacitance type and infrared type according to its technical principle.
At present, resistive touch screens are widely used in embedded systems. Resistance contact
Touch screen is a multilayer composite film, with a layer of glass or plexiglass as the base layer and a transparent coating on the surface.
The transparent conductive layer is covered with a plastic layer, and its inner surface is also coated with the transparent conductive layer.
There are many tiny transparent isolation points between the two conductive layers to isolate them. ITO is often used in industry.
(indium tin oxide) as the conductive layer. According to the number of signal lines, the resistive touch screen is divided into four parts.
Line, five lines, six lines, etc. The more signal lines, the more complex the technology and the more accurate the coordinate positioning.
That's true. The basic principles of all resistive touch screens are similar. When touching the screen, the two are usually insulated.
The conductive layer of this layer has contacts at the contact points. After the controller detects this connection, because it
One conductive layer is connected with a uniform voltage of 5V in the Y-axis direction, and the other conductive layer is controlled by the contact voltage.
The circuit carries out A/D conversion, and after obtaining the voltage value, the Y-axis coordinate of the touch point can be obtained by comparing it with 5V.
Get the coordinates of the x axis [15]
. This paper uses a four-wire resistive touch screen.
S3C2440 provides 8 A/D analog inputs, 4 of which are multiplexed with the touch screen. If XP,
When the four pins XM, YP and YM are not used for touch screen input, they can be used as ordinary A/D converters.
Use. The touch screen interface of S3C2440 has four working modes:
(1) Normal conversion mode: This mode is similar to the general A/D conversion mode. This pattern can be found in.
Set 1 in ADCCON(ADC control register) and complete it in ADCDAT0 (data register 0).
Data reading and writing.
(2)X/Y coordinate transformation: The touch screen controller supports two transformation methods, and the X/Y coordinates are as follows
X/Y coordinate conversion and automatic conversion. Every conversion is to write the x coordinate into ADCDAT0 in x mode.
An interrupt is generated; In y mode, write the y coordinate into ADCDAT 1, and then generate an interrupt.
(3) Automatic conversion of X/Y coordinates: In this mode, the touch screen controller converts the X of the touch point in turn.
Coordinates and y coordinates. When both X and Y coordinates are converted, the interrupt controller will generate an interrupt.
(4) Waiting for interrupt mode: When the stylus is pressed, the touch screen generates an interrupt (INT_TC). wait for
Interrupt mode must set register rADCTSC to 0xd3；; After the touch screen controller generates an interrupt,
This mode must be cleared.
The touch screen used in this design is provided by Guangzhou Youhao Arm Company, and an LCD screen is added.
AA084VC03 provides an external interface together with LCD. AA084VC03 is from Mitsubishi, Japan.
The company's 8.4-inch TFT-LCD has a resolution of 640x480 and a color of 262K. This touch screen is a four-wire resistor.
Touch screen, using the touch screen control unit of S3C2440 can greatly simplify the circuit design. Specific circuit
See Figure 2-6 in the next section. AM29LV800D
See if it works for you.